System for processing data structures in a node of a communication network

• US 5,568,478 A
• Filed: 07/13/1994
• Issued: 10/22/1996
• Est. Priority Date: 07/14/1993
• Status: Expired due to Fees

• Current Assignee: Ascom Tech AG, Atecom GmbH
• Original Assignee: Ascom Tech AG, Atecom GmbH
• Inventors: van Loo, Gerrit J. Jr., Noll, Joachim, Schwope, Andreas
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): BLUM, RUSSELL
• Application Number:
  US08/275,000
• Time in Patent Office: 832 Days
• Field of Search: 370/58.1, 370/58.2, 370/58.3, 370/60, 370/60.1, 370/79, 370/82, 370/83, 370/94.1, 370/94.2
• US Class Current: 370/392
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/557 Error correction, e.g. fault recovery or fault tolerance
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

All the information sections of a processed data structure, including pre-header, tail and extra section, header and payload, can be selectively copied in a node of a communication network by means of a copy mask (12) associated with a copy block (11). A combination of an insert block (14) and an insert mask (15) is used for selectively writing to all the information sections in the data structure. In order to increase the capacity of the data structure, the length of the pre-header or tail can be increased. In the path between an input interface (10) and the insert block (14) there is an adjustable delay block (13) into which the data structure can be copied as a whole. A microprocessor (25) is coupled to all the processing units (10)-(17) and (22)-(24) of the system and serves for presetting the two masks for selecting the information to be copied and inserted.

Claims

1. In a communication network containing a plurality of nodes for switching binary data structures, a method of processing a binary data structure comprising an ATM (asynchronous transfer mode) cell,

said ATM cell consisting of a header and a payload, said binary data structure further comprising at least one additional information section selected from a group consisting of a tail following said payload and a parallel information field extending in parallel to said ATM cell;

said method comprising the following steps;

a) inputting said binary data structure via an input interface into one of said nodes;

b) selective copying of said header, said payload and said at least one additional information section by a first mask;

c) selectively writing said header, said payload and said at least one additional information section by means of a second mask;

d) outputting said binary data structure via an output interface.

2. The method of claim 1 wherein said at least one additional information section is a parallel information field extending in parallel to said ATM cell.

3. The method of claim 1 or 2, wherein the data structure is delayed undivided after copying until all the data required for writing in step c) are available.

4. The method of claim 3, wherein the data required in step c) are made available defending on the selective copying of at least one information section.

5. The method of claim 4, characterized in that the header, payload, and additional information section selectively read in step b) are at least partially used as a pointer for an internal memory and in that data from the internal memory as indicated by the pointer are selectively written in step c).

6. The method of claims 1 or 2, characterized in that in an initialization phase before processing of the binary data structure, the input and output interfaces are selected, a first mask used for selective copying and a second mask used for selective writing are preset to copying and writing, respectively, of at least one information section from said payload and/or said header of the ATM cell, said tail and/or said parallel information field, and in that at least one internal source and/or at least one external source is selected as a data source for the writing operation.

7. In a communication network containing a plurality of nodes, a system for processing a binary data structure,

said binary data structure comprising an ATM (asynchronous transfer modes) cell consisting of a header and a payload,

said binary data structure further comprising at least one additional information section selected from a group consisting of a tail following said payload and a parallel information field extending in parallel to said ATM cell,

said system associated with one of said nodes for processing said ATM cell and comprising:

a) an input interface for receiving said binary data structure,

b) a copy means having a first masking means for selectively copying said header, said payload and said at least one additional information section of said data structure,

c) an insert means having a second masking means for selectively writing said payload, said header and said at least one additional information section, and

d) an output interface for outputting said binary data structure,

whereby each of said header, said payload, and said at least one additional information section can be selectively copied and written independently from each other.

8. The system of claim 7, wherein said at least one additional information section is a parallel information field.

9. The system of claim 7 or 8, further comprising a delay means into which said data structure can be copied undivided is provided between said input interface and said insert means.

10. The system of claim 9, wherein said delay means is provided with means for adjusting the delay.

11. The system of claim 10, comprising a microprocessor coupled to said input interface, said copy means, said insert means, said output interface, and said delay means for selecting said input and output interfaces, for resetting said copy and insert means, for adjusting said first and second masking means for selection of information to be copied and inserted and for presetting a delay time for said delay means.

12. The system of claim 11, comprising an internal memory connected, on the one hand, via a first demultiplexer to said first masking means and, on thee other hand, via a second demultiplexer to said second masking means and wherein a pointer is set in said memory by means of said first masking means and

wherein an entry at a position indicated by said pointer is inserted into said binary data structure via said second masking means.

13. In a communication network containing a plurality of nodes, a system for processing a binary data structure

said binary data structure comprising an ATM (asynchronous transfer mode) cell consisting of a header and a payload,

said binary data structure further comprising a pre-header and at least one additional information section selected from a group consisting of a tail following said payload and a parallel information field extending in parallel to said ATM cell and said pre-header,

said system being associated with one of said nodes for processing said ATM cell and comprising:

a) an input interface for receiving said binary data structure,

b) a copy means having a first masking means for selectively copying said header, said payload, said pre-header and said at least one additional information section of said data structure,

c) an insert means having a second masking means for selectively writing said payload, said header, said pre-header and said at least one additional information section, and

d) an output interface for outputting said binary data structure,

whereby each of said header, said payload, said pre-header, and said at least one additional information section can be selectively copied and written independently from each other.

14. The system of claim 13, wherein said at least one additional information section is a parallel information field.

15. The system of claim 13 or 14, further comprising a delay means into which said data structure can be copied undivided is provided in the path between said input interface and said insert means.

16. The system of claim 15, wherein said delay means is provided with means for adjusting the delay.

17. The system of claim 16, comprising a microprocessor coupled to said input interface, said copy means, said insert means, said output interface, and said delay means for selecting said input and output interfaces, for resetting said copy and insert means, for adjusting said first and second masking means for selection of information to be copied and inserted, and for presetting a delay time for said delay means.

18. The system of claim 17, comprising an internal memory connected, on the one hand, via a first demultiplexer to said first masking means and, on the other hand, via a second demultiplexer to said second masking means and wherein a pointer is set in said memory by means of said first masking means and

wherein an entry at a position indicated by said pointer is inserted into said binary data structure via said second masking means.