Method and device for transferring data in a TDMA system

• US 5,568,490 A
• Filed: 06/10/1994
• Issued: 10/22/1996
• Est. Priority Date: 06/10/1994
• Status: Expired due to Term

• Current Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Original Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Inventors: McNinch, Wayne, Weaver, Chris, Wendling, Daniel
• Primary Examiner(s): Hsu, Alpus H.
• Assistant Examiner(s): NGO, RICKY QUOC
• Application Number:
  US08/258,160
• Time in Patent Office: 865 Days
• Field of Search: 370/95.3, 370/81, 370/51, 370/85.1, 370/95.2, 370/119, 370/77, 370/56, 370/85.2, 370/85.7, 370/85.9, 370/85.11, 370/85.13, 370/85.6, 395/11, 395/275, 395/325, 395/375, 395/425, 395/725, 395/775, 379/333, 379/334, 379/93, 379/94, 364/130, 364/131, 364/133, 364/134, 364/138, 364/230, 364/232.22, 364/232.8, 375/219, 375/222
• US Class Current: 370/347
• CPC Class Codes: H04J 3/1605 Fixed allocated frame structures

Abstract

A data transfer device for transferring data between a plurality of digital signal processors in a system utilizing time division multiple access techniques. The data transfer device includes a system controller coupled to a bus network, a plurality of dual port random access memories, and a direct memory access controller. Each dual port random access memory device includes a first input/output port coupled to one of the plurality of digital signal processors, and a second input/output port coupled to the bus network. Each of the plurality of digital signal processors can access the dual port random access memory device coupled thereto during a first predefined time within a TDMA cycle. During a second predefined time period within the same TDMA cycle, the direct memory access controller, under control of the system controller, transfers data directly between the dual port random access memory devices. During a third predefined time period within the same TDMA cycle, the system controller can access the dual port random access memory devices coupled thereto.

Claims

1. A device for transferring data between a plurality of digital signal processors in a system utilizing time division multiple access, said device comprising:

a system controller coupled to a bus network;

a plurality of dual port random access memory devices, each of which has a first port coupled to one of said plurality of digital signal processors and a second port coupled to said bus network; and

a linked list direct memory access controller for transferring data between said dual port random access memory devices, said direct memory access controller coupled to said bus network and controlled by said system controller;

said system controller further comprising a timing generation circuit for generating a first periodic signal, said first periodic signal being coupled to each of said plurality of digital signal processors and said memory access controller, said first periodic signal defining the start of said first predefined time period; and

a delay circuit for delaying said first periodic signal a predetermined amount so as to create a start signal defining the beginning of said second predefined time period, said start signal being coupled to said memory controller.

2. A device for transferring data between a plurality of digital signal processors according to claim 1, wherein said system controller and said memory controller are formed in a single integrated circuit.

3. A device for transferring data between a plurality of digital signal processors according to claim 2, wherein said linked list direct memory access controller allows the transfer of blocks of data between said dual port random access memory devices in a single transfer.

4. A device for transferring data between a plurality of digital signal processors according to claim 1, wherein said system controller comprises a memory map which includes said dual port random access memory devices coupled to said plurality of digital signal processors.

5. A device for transferring data between a plurality of digital signal processors according to claim 1, further comprising a timing bus coupled between said timing generation circuit, said delay circuit and said plurality of digital signal processors so as to allow said first periodic signal to be transmitted to said plurality of digital signal processors and said memory controller.

6. A device for transferring data between a plurality of digital signal processors according to claim 1, wherein at least one of said plurality of digital signal processors comprises a memory map which includes said dual port random access memory device coupled thereto.

20. A device for transferring data between a plurality of digital signal processors according to claim 1, further comprising an adjustment circuit for synchronizing the first periodic signal with a periodic signal input from an external source.

7. A method for transferring data between a plurality of digital signal processors in a system utilizing time division multiple access, comprising:

allocating by a system controller a first predefined time period within a TDMA cycle in which each of said plurality of digital signal processors access a dual port random access memory device coupled thereto,

allocating by the system controller a second predefined time period within said TDMA cycle in which a linked list direct memory access controller transfers data between said dual port random access memory devices, and

allocating by the system controller a third predefined time period within said TDMA cycle in which the system controller accesses said dual port random access memory devices coupled to said plurality of digital signal processors.

8. The method of claim 7, wherein said first, second and third predefined time periods do not coincide with one another.

9. The method of claim 7, wherein said linked list direct memory access controller transfers blocks of data at the same time.

10. The method of claim 7, wherein said system controller comprises a memory map which includes said dual port random access memory devices coupled to said plurality of digital signal processors.

11. The method of claim 7, wherein each of said plurality of digital signal processors comprises a memory map which includes said dual port random access memory device coupled thereto.

12. The method of claim 8, further comprising generating a periodic slot clock signal which defines the start of a TDMA cycle and said first predefined time period.

13. The method of claim 12, further comprising delaying said first periodic signal a predetermined amount so as to create a start signal defining the beginning of said second predefined time period, said start signal being coupled to said memory controller.

14. The method of claim 12, wherein said periodic slot clock signal can be delayed up to one TDMA cycle so as to allow said periodic slot clock signal to synchronize with a periodic clock signal received from an external source such that the duration of said first, second and third predefined time periods are maintained.

15. The method of claim 7, wherein the duration of said first, second and third predefined time periods are variable in accordance with system requirements.

16. A device for transferring data between a plurality of digital signal processors in a time division multiple access system, said device comprising:

a bus network;

a system controller coupled to said bus network, said system controller further comprising a timing generation circuit for generating a first periodic signal, said first periodic signal being said to each of said plurality of digital signal processors, said first periodic signal defining the start of a first predefined time period;

a plurality of random access memory devices, each of which is coupled to one of said plurality of digital signal processors and to said bus network;

a memory controller for transferring data between said random access memory devices, said memory controller coupled to said bus network and controlled by said system controller;

a delay circuit for delaying said first periodic signal for a predetermined amount of time so as to create a start signal defining the beginning of a second predefined time period, said start signal being coupled to said memory controller; and

a timing bus coupled between said timing generation circuit, said delay circuit and said plurality of digital signal processors so as to allow said first periodic signal to be transmitted to said plurality of digital signal processors and said memory controller.

17. The device of claim 16, wherein said memory controller comprises a direct memory access controller.

18. The device of claim 16, wherein at least one of said digital signal processors encodes and decodes speech data.

19. An apparatus for receiving a plurality of telephone signals carried by a plurality of telephone lines and generating a concentrated telephone signal to be transmitted by an antenna over a radio communication link comprising:

a telephone line circuit module receiving the plurality of telephone lines and producing the plurality of respective telephone signals;

a first digital signal processor comprising an encoder receiving the plurality of telephone signals from the telephone line circuit and producing encoded telephone signals;

a system controller coupled to a bus network, said system controller receiving the encoded telephone signals and generating a concentrated telephone signal having a plurality of speech slots, each of the encoded telephone signals assigned to at least one of the speech slots;

a second digital signal processor comprising a modem responsive to said system controller, said modem modulating said concentrated telephone signal to produce a modulated signal;

a plurality of dual port random access memory devices, each of which has a first port coupled to said digital signal processors and a second port coupled to said bus network;

a memory controller for transferring data between said dual port random access memory devices, said memory controller coupled to said bus network and controlled by said system controller; and

a transceiving module coupled to the antenna and responsive to said modem, said transceiving module transmitting said modulated signal over the radio communication link via the antenna.