Area efficient high voltage MOSFETs with vertical RESURF drift regions

• US 5,569,949 A
• Filed: 05/31/1995
• Issued: 10/29/1996
• Est. Priority Date: 09/02/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Malhi, Satwinder
• Primary Examiner(s): MEIER, STEPHEN D
• Application Number:
  US08/455,785
• Time in Patent Office: 517 Days
• Field of Search: 257/301, 257/302, 257/394, 257/397
• US Class Current: 257/397
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

A high voltage power transistor cell is developed that provides improved RDSon performance without sacrificing breakdown performance through utilization of trench based transistor technology. A source, drain and trench are formed within a substrate. A gate is formed or the surface over a spacing between the source and the trench. A drift region is formed around the trench. An isolation region may optionally be added allowing electrical isolation between the source and the substrate. The lateral current flow feature allows multiple high voltage power transistors, electrically isolated from one another, to exist on a single semiconductor chip. The drift region formed around the trench provides RESURF transistor characteristics without sacrificing die area.

Claims

1. A lateral power transistor, comprising:

a source region formed in a semiconductor substrate;

a drain region formed in the semiconductor substrate, the drain region being laterally spaced from the source region;

a trench disposed between the source region and the drain region, the trench abutting the drain region and being laterally spaced from the source region;

a gate formed on the semiconductor substrate above the lateral spacing between the source region and the trench, the lateral spacing forming a channel region; and

a drift region formed around the trench, making contact with the drain region and the channel region, wherein the drift region surrounding the trench provides an extended length drift region, thereby providing RESURF transistor performance while simultaneously reducing transistor pitch.

2. The lateral power transistor of claim 1, further comprising isolation means formed between the source region and the semiconductor substrate, thereby providing electrical isolation between the source region and the semiconductor substrate, thereby allowing a plurality of lateral power transistors to operate independently of one another on a single semiconductor die.

3. The lateral power transistor of claim 2 wherein the isolation means comprises:

a body region formed below the source region; and

an isolation region formed between the body region and the semiconductor substrate.

4. A power transistor, comprising:

a trench formed in a semiconductor substrate;

an oxide formed in the trench;

a drain region formed in the oxide, extending form a top surface of the power transistor to the bottom of the trench;

a source region formed in the semiconductor substrate, the source region being laterally spaced from the trench;

a gate formed on the semiconductor substrate above the lateral spacing between the source region and the trench, the lateral spacing between the source region and the trench forming a channel region; and

a drift region formed around the trench in the semiconductor substrate, making contact with drain region at the bottom of the trench and the channel region, wherein the drift region provides RESURF transistor characteristics while simultaneously decreasing transistor pitch.

5. The power transistor of claim 4, further comprising:

a second source region formed in the semiconductor substrate on the side of the trench opposite the source region, the second source region being laterally spaced from the trench; and

a second gate formed on the semiconductor substrate above the second lateral spacing between the trench and the second source region, the second lateral spacing forming a second channel region, the second channel region making contact with the drift region surrounding the trench, whereby the source region and the second source region share the same drain region, thereby deceasing transistor area for multiple source power transistors.

6. The power transistor of claim 4, further comprising:

isolation means formed between the source region and the semiconductor substrate, thereby

providing electrical isolation between the source region and the semiconductor substrate, thereby

allowing a plurality of lateral power transistors to operate independently of one another on a single semiconductor die.

7. The lateral power transistor of claim 6 wherein the isolation means comprises:

a body region formed below the source region; and

an isolation region formed between the body region and the semiconductor substrate.