Semiconductor device with a semiconductor element provided in a mesa structure

• US 5,569,952 A
• Filed: 09/30/1994
• Issued: 10/29/1996
• Est. Priority Date: 10/01/1993
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Dekker, Ronald, Maas, Henricus G. R., Gravesteijn, Dirk J., Versleijen, Martinus P. J. G.
• Primary Examiner(s): BROWN, PETER T
• Application Number:
  US08/316,304
• Time in Patent Office: 760 Days
• Field of Search: 257/152, 257/164, 257/166, 257/170, 257/331, 257/341, 257/579, 257/584, 257/586, 257/587, 257/600, 257/734, 257/773, 257/622-626, 257/578
• US Class Current: 257/579
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/7325 having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A semiconductor device includes a semiconductor body (1) having a semiconductor element with connection points (2, 3) which adjoins a surface (4) of the semiconductor body (1) and is laterally insulated and surrounded by a first depression (5) in the surface (4), which depression (5) is provided with a wall (6) and a bottom (7), while the surface (4) of the semiconductor body (1) and the wall (6) and bottom (7) of the depression (5) are covered with an insulating layer (8). The connection points (2, 3) are provided in the insulating layer (8) on the surface (4) of the semiconductor body (1) and are connected to conductor tracks (10, 11) which connect the connection points (2, 3) across a wall (6) to connection surfaces (12, 13) associated with the connection points (2, 3) and situated on the bottom (7). It is found in practice that, in the case of progressive miniaturization, the manufacture of such devices leads to rejects caused by short-circuits between connection surfaces (12, 13). According to the invention, one or several further depressions (50) surrounded by the first depression (5) is/are present in the surface (4) of the semiconductor body (1), while only one connection surface (12, 13) is present on the bottom (7, 57) of each of the first and further depressions (5, 50), which connection surface is connected to a connection point (2, 3) on the surface (4) of the semiconductor body (1) via a conductor track (10, 11). Short-circuits are found to take place in the known semiconductor devices on a wall (6) of the depression (5) when there are more than one conductor tracks (10, 11) on this wall (6). Here, however, only one conductor track (10 or 11) is present on the wall (6, 56 of the depression (5, 50), so short-circuits with other conductor tracks on the wall (6, 56) cannot arise.

Claims

1. A semiconductor device with a semiconductor body comprising a semiconductor element with connection points, which semiconductor element adjoins a surface of the semiconductor body and is laterally insulated and surrounded by a first depression in the surface, which depression is provided with a first wall and a first bottom, the surface of the semiconductor body and the first wall and the first bottom of the depression being covered with an insulating layer, and the connection points being provided in the insulating layer on the surface of the semiconductor body and being connected to conductor tracks which connect the connection points across one of said first and a second wall to connection surfaces belonging to the connection points and situated on one of said first and a second bottom, wherein a further depression having said second wall and said second bottom is present in the surface of the semiconductor body and surrounded by the first depression, a connection surface being present on each of said first and said second bottom, each connection surface being connected to one of said connection points on the surface of the semiconductor body through one of said conductor tracks.

2. A semiconductor device as claimed in claim 1, characterized in that the conductor tracks comprise gold.

3. A semiconductor device as claimed in claims 1, characterized in that the walls of the depressions enclose an angle of more than 50°

with the bottoms of the depressions.

4. A semiconductor device as claimed in claim 1, characterized in that the conductor tracks are patterned only on the surface of the semiconductor body and on the bottom of the depressions and comprise an unpatterned conductive layer on the walls.

5. A semiconductor device as claimed in claim 1, characterized in that a further connection point of the semiconductor element provided with a connection surface is present on the bottom of a selected depression.

6. A semiconductor device as claimed in claims 1, characterized in that the semiconductor element comprises a plurality of semiconductor sub-elements which are interconnected by dams, the semiconductor sub-elements and the dams enclosing the further depression.

7. A semiconductor device as claimed in claim 1, characterized in that the semiconductor element comprises a transistor with base and emitter contacts as the connection points, the connection surface for the emitter contact lying in the first depression and the connection surface for the base contact in the further depression.