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BiCMOS multiplexers and crossbar switches

  • US 5,570,059 A
  • Filed: 01/20/1995
  • Issued: 10/29/1996
  • Est. Priority Date: 01/08/1993
  • Status: Expired due to Term
First Claim
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1. A crossbar switch, comprising:

  • a plurality of high speed signal inputs for receiving high speed data signals;

    a first multiplexer having a plurality of data inputs equal in number to the number of said plurality of high speed signal inputs and each coupled to one of said plurality of high speed signal inputs, said first multiplexer having a shared data output, said first multiplexer comprised of a plurality of switching devices each of which is coupled to one of said plurality of high speed signal inputs via a corresponding one of said data inputs of said first multiplexer, and each of said plurality of switching devices having an enabling circuit coupled thereto for receiving a steering signal assigned to that switching device so as to individually enable said switching device, said enabling circuitry controlled by a steering signal assigned to that switching device so as to be able to drive said shared data output of said first multiplexer in accordance with data received at the corresponding high speed signal input to which said switching device is coupled;

    one or more other multiplexers, each having a corresponding plurality of data inputs equal in number to the number of said high speed signal inputs, each of said plurality of data inputs of said one or more other multiplexers coupled to one of said plurality of high speed signal inputs, and each of said one or more other multiplexers having a shared data output, each of said one or more other multiplexers comprised of a plurality of switching devices each of which has a data input which is coupled to a data input of the one of said one or more other multiplexers of which said switching device is a part, each of said switching devices of said one or more other multiplexers including an enabling circuit coupled thereto, said enabling circuit controlled by a steering signal assigned to that switching device so as to individually enable the switching device to which said enabling circuit is coupled in response to said steering signal assigned to said switching device, so as to control said switching device to drive the shared data output of the multiplexer of which the switching device so enabled is a part in response to the data received at the high speed signal input to which said switching device is coupled, such that by proper manipulation of said steering signals for said first multiplexer and said one or more other multiplexers, each of the shared outputs can be driven with signals received at any one of said high speed signal inputs so long as no more than one high speed signal input is used to drive any shared data output at any particular time;

    and wherein each of said switching devices coupled to one of said plurality of data inputs in said first multiplexer and each of said switching devices coupled to one of said plurality of data inputs of said one or more other multiplexers comprises a high speed, differential pair of bipolar transistors controlling data flow in the data path between said high speed signal inputs and said shared data outputs and wherein each said differential pair of bipolar transistors has a common emitter node and is integrated on an integrated circuit with the corresponding enabling circuit to which said switching device is coupled, and wherein each said enabling circuit is comprised of integrated CMOS transistors which are coupled to said common emitter node of the differential pair of bipolar transistors to which said enabling circuit is coupled, said CMOS transistors for selectively coupling either a first voltage to said common emitter node when the steering signal assigned to said switching device is in a first logical state so as to enable said switching device or coupling a second voltage to said common emitter node when said steering signal is in a second logical state so as to disable said switching device, thereby keeping said CMOS transistors of said enabling circuit of each switching device out of the high speed signal data path between any of said high speed signal inputs and any of said shared data outputs.

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