BiCMOS multiplexers and crossbar switches

• US 5,570,059 A
• Filed: 01/20/1995
• Issued: 10/29/1996
• Est. Priority Date: 01/08/1993
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Dyna Logic Corporation
• Inventors: Vora, Madhukar B., West, Burnell G.
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US08/375,303
• Time in Patent Office: 648 Days
• Field of Search: 327/403-417, 327/432, 327/433, 326/109, 326/110
• US Class Current: 327/415
• CPC Class Codes: H03K 17/6257 with several inputs only combined with selecting means
• CPC Class Codes: H03K 17/6285 with several outputs only combined with selecting means
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence

Abstract

A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

Claims

1. A crossbar switch, comprising:

a plurality of high speed signal inputs for receiving high speed data signals;

a first multiplexer having a plurality of data inputs equal in number to the number of said plurality of high speed signal inputs and each coupled to one of said plurality of high speed signal inputs, said first multiplexer having a shared data output, said first multiplexer comprised of a plurality of switching devices each of which is coupled to one of said plurality of high speed signal inputs via a corresponding one of said data inputs of said first multiplexer, and each of said plurality of switching devices having an enabling circuit coupled thereto for receiving a steering signal assigned to that switching device so as to individually enable said switching device, said enabling circuitry controlled by a steering signal assigned to that switching device so as to be able to drive said shared data output of said first multiplexer in accordance with data received at the corresponding high speed signal input to which said switching device is coupled;

one or more other multiplexers, each having a corresponding plurality of data inputs equal in number to the number of said high speed signal inputs, each of said plurality of data inputs of said one or more other multiplexers coupled to one of said plurality of high speed signal inputs, and each of said one or more other multiplexers having a shared data output, each of said one or more other multiplexers comprised of a plurality of switching devices each of which has a data input which is coupled to a data input of the one of said one or more other multiplexers of which said switching device is a part, each of said switching devices of said one or more other multiplexers including an enabling circuit coupled thereto, said enabling circuit controlled by a steering signal assigned to that switching device so as to individually enable the switching device to which said enabling circuit is coupled in response to said steering signal assigned to said switching device, so as to control said switching device to drive the shared data output of the multiplexer of which the switching device so enabled is a part in response to the data received at the high speed signal input to which said switching device is coupled, such that by proper manipulation of said steering signals for said first multiplexer and said one or more other multiplexers, each of the shared outputs can be driven with signals received at any one of said high speed signal inputs so long as no more than one high speed signal input is used to drive any shared data output at any particular time;

and wherein each of said switching devices coupled to one of said plurality of data inputs in said first multiplexer and each of said switching devices coupled to one of said plurality of data inputs of said one or more other multiplexers comprises a high speed, differential pair of bipolar transistors controlling data flow in the data path between said high speed signal inputs and said shared data outputs and wherein each said differential pair of bipolar transistors has a common emitter node and is integrated on an integrated circuit with the corresponding enabling circuit to which said switching device is coupled, and wherein each said enabling circuit is comprised of integrated CMOS transistors which are coupled to said common emitter node of the differential pair of bipolar transistors to which said enabling circuit is coupled, said CMOS transistors for selectively coupling either a first voltage to said common emitter node when the steering signal assigned to said switching device is in a first logical state so as to enable said switching device or coupling a second voltage to said common emitter node when said steering signal is in a second logical state so as to disable said switching device, thereby keeping said CMOS transistors of said enabling circuit of each switching device out of the high speed signal data path between any of said high speed signal inputs and any of said shared data outputs.

2. A high speed multiplexer comprising:

an input for coupling to a low voltage supply;

an input for coupling to a high voltage supply;

a differential input for receiving a high speed, differential data signal;

a plurality of differential outputs at which a high speed, differential output signal can appear;

a bipolar switching circuit coupled to said inputs for coupling to said high and low voltage supplies, and coupled to said differential input and to said plurality of differential outputs, said bipolar switching circuit for controlling data flow through a high speed data path, said high speed data path including first and second complementary inputs of said differential input and a plurality of differential outputs;

and wherein said bipolar switching circuit comprises a plurality of high speed differential amplifiers, each said differential amplifier having a pair of complementary data inputs coupled to said differential input and having a pair of complementary data outputs coupled to one of said plurality of differential outputs, and each said differential amplifier having a common power return node, and each said differential amplifier including a CMOS enabling circuit coupled to said common power return node of that particular differential amplifier and having an enable input for receiving a digital steering signal, said CMOS enabling circuit for selectively coupling said common power return node of that particular differential amplifier to either said input for coupling to said low voltage supply or to said input for coupling to said high voltage supply depending upon the logic state of said steering signal, and wherein the state of said steering signal of any particular differential amplifier controls whether that particular differential amplifier is enabled or disabled, and wherein each said differential amplifier is coupled to receive high speed data signals from said first and second complementary inputs of said differential input and, when enabled, for coupling said high speed, differential data signals received from said differential input to said complementary data outputs of that particular differential amplifier and thence to the differential output to which said complementary data outputs are coupled; and

wherein each said CMOS enabling circuit included with each said differential amplifier has a pair of complementary CMOS switching transistors comprising a CMOS transistor of a first type coupling said common power return node of the differential amplifier of which said CMOS enabling circuit is a part to said input for coupling to a high voltage supply and having a gate terminal coupled to said enable input, and a CMOS transistor of a second type coupling said common power return node of the differential amplifier of which said CMOS enabling circuit is a part to said input for coupling to a low voltage supply and having a gate terminal coupled to said enable input, such that when said steering signal for a particular differential amplifier is in a state to enable that differential amplifier, said CMOS transistor of said second type is turned on and said CMOS transistor of said first type is turned off thereby connecting said common power return node to said input for coupling to said low voltage supply and enabling operation by said differential amplifier, and, when said steering signal for a particular differential amplifier is in a logic state to disable that particular differential amplifier, said CMOS transistor of a first type is turned on and said CMOS transistor of a second type is turned off thereby coupling said common power return node to said input for coupling to a high voltage supply thereby disabling operation of said differential amplifier.

3. A method of switching high speed data signals, comprising:

receiving said high speed data signals at a high speed data input;

selectively coupling said high speed data signals to any one of a plurality of high speed data outputs each of which is an output of one of a plurality of high speed switching devices, each of said high speed switching devices having a data input coupled to receive the same high speed data signals received at said high speed data input, and each of said high speed switching devices having a node therein which if coupled to a first voltage source will disable said high speed switching device thereby preventing coupling of said high speed data signals received at said high speed data input to the high speed data output of that particular high speed switching device, and, if coupled to a second voltage source, will enable said high speed switching device thereby enabling coupling of said high speed data signals received at said high speed data input to the high speed data output of that particular high speed switching device, and wherein said node in each said high speed switching device does not appreciably change in voltage with fluctuations of voltage in said high speed data signals received at said high speed data input or with fluctuations of voltage in said high speed data signals output at said high speed data output; and

CMOS enabling circuitry for each said high speed switching device and having an enable signal input for each said high speed switching device for receiving an enable signal associated with the corresponding high speed switching device, each said CMOS enabling circuit for selectively coupling said node of the corresponding high speed switching device to said first voltage source to disable said high speed switching device when said enable signal is in a first logic state, and for selectively coupling said node to said second voltage source to enable said high speed switching device when said enable signal is in a second logic state.