Phase generator

• US 5,570,392 A
• Filed: 06/01/1995
• Issued: 10/29/1996
• Est. Priority Date: 08/14/1992
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Chester, David B., Young, William R.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): GHEBRETINSAE, TEMESGHEN
• Application Number:
  US08/456,859
• Time in Patent Office: 516 Days
• Field of Search: 375/326, 375/327, 375/371, 375/373, 375/374, 375/308, 327/141, 327/157, 327/159, 332/104
• US Class Current: 375/308
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0021 Decimation, i.e. data rate reduction techniques H04B1/0025 takes precedence
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04J 1/05 using digital techniques
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence

Abstract

A digital down converter with a programmable mixing down frequency and a programmable extraction bandwidth uses a ROM based sin/cos generator plus a programmable high decimation filter followed by a gain compensating scaling multiplier and a fixed FIR filter. Output format options are also programmable, and programming commands are serially loaded into registers. Various components may be isolated for efficient testing and also subsystem operation.

Claims

1. A phase generator, comprising:

a phase accumulator;

a phase increment accumulator coupled to said phase accumulator;

a minimum phase increment register coupled to said phase increment accumulator;

a maximum phase increment register coupled to said phase increment accumulator;

a delta phase increment register coupled to said phase increment accumulator; and

a controller intercoupling said accumulators and registers with said phase increment accumulator coupled though a first adder/subtractor to said phase accumulator and with the following modes of coupling;

(1) normal mode couples said minimum phase increment register to said phase increment accumulator whereby the contents of said phase accumulator is successively incremented by the contents of said phase increment accumulator which are derived from said minimum phase increment register;

(2) chirp up mode couples said minimum phase increment register to said phase increment accumulator, said delta phase increment register through a second adder/subtractor to said phase increment accumulator, and said maximum phase register through a comparator to said phase increment accumulator whereby the contents of said phase accumulator is successively incremented by the contents of said phase increment accumulator which are successively incremented by the contents of said delta phase register from an initial contents equal to the contents of said minimum phase register and repeating until the contents of said phase increment accumulator exceed the contents of samd maximum phase register;

(3) chirp down mode couples said maximum phase increment register to said phase increment accumulator, said delta phase increment register through said second adder/subtractor to said phase increment accumulator, and said minimum phase register through a comparator to said phase increment accumulator whereby the contents of said phase accumulator is successively incremented by the contents of said phase increment accumulator which are successively decremented by the contents of said delta phase register from an initial contents equal to the content of said maximum phase register and repeating until the contents of said phase increment accumulator diminish below the contents of said minimum phase register, and

(4) chirp up-down mode couples said minimum phase increment register to said phase increment accumulator, said delta phase increment register through said second adder/subtractor to said phase increment accumulator, and both said maximum phase register and said minimum phase register through a comparator to said phase increment accumulator whereby the contents of said phase accumulator may be successively incremented by the contents of said phase increment accumulator which are successively (i) incremented by the contents of said delta phase register from an initial contents equal to the contents of said minimum phase register, and when the contents of said phase increment accumulator exceed the contents of said maximum phase register (ii) decremented by the contents of said delta phase register, and when the contents of said phase increment accumulator are diminished below the contents of said minimum phase register repeating from (i).

2. The phase generator of claim 1, further comprising:

a phase offset register coupled to said phase accumulator by said controller, whereby the initial contents of said phase accumulator is set equal to the contents of said phase offset register.

3. The phase generator of claim 1, wherein:

said controller couples said phase increment accumulator through said first adder/subtractors for decrementing rather than incrementing said the contents of said phase accumulator.