Method of making poly LDD self-aligned channel transistors

• US 5,571,738 A
• Filed: 01/06/1995
• Issued: 11/05/1996
• Est. Priority Date: 09/21/1992
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Krivokapic, Zoran
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/369,766
• Time in Patent Office: 669 Days
• Field of Search: 437/44, 437/45, 437/56, 437/57, 437/58, 437/67, 437/984, 148/DIG. 50
• US Class Current: 438/291
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

Short channel MOS devices are provided with two distinct doped polysilicon contacts: (a) doped polysilicon layers in contact with the source or drain regions (the LDD regions) and extending underneath the oxide region to abut the oxide liner of the trench sidewalls; and (b) polysilicon source and drain contacts in contact with the doped polysilicon layers. The shallow channel doping region is self-aligned with the lightly doped source and drain regions; this ensures vertically engineered profiles that give high punchthrough voltages and an excellent short channel control. The use of the doped polysilicon layers ensures self-alignment of source/drain diffusions and channel and prevents etching of TEOS in the trenches, which prevents exposure of trench sidewalls and formation of parasitic devices in the sidewalls. Further, use of doped polysilicon layers to form the LDD regions by diffusion results in high currents and shallow junctions. The devices also include an insulation spacer that separates the gate electrode from the oxide region between the source and drain contacts and the gate electrode, the insulation spacer preferably made of a nitride. To relieve stress, a thin oxide layer is provided between the insulation spacer and the oxide region. The insulation spacers increase drive currents and move the peak electric field under the spacers, thereby improving device reliability. The insulation spacers also make it possible to define effective channel lengths, thereby avoiding the use of advanced lithography.

Claims

1. In a method for making a trench isolated FET wherein an active region in a silicon substrate is isolated by a trench and wherein wells of a first conductivity type in said substrate have separated source and drain regions having top surfaces therein, both said source and drain regions being contiguous to and separated by a gate region, and where in a completed said trench isolated FET said gate region overlies said top surfaces of said source and drain regions adjacent to said contiguous edge by a first distance, the improvement comprising:

(a) layering said top of said source and drain regions of said FET with a first poly layer;

(b) creating said trench having sidewalls around said source and drain regions by etching into said underlying Si and exposing the edge of said first poly layer without removing said first poly layer overtop said source and drain region;

(c) oxidizing said sidewalls of said trench including oxidizing said exposed edge of said first poly layer to form an isolation oxide liner around said periphery of said active region including said source and drain regions, said first poly layer and said trench sidewall having an intersection;

(d) depositing an oxide layer over top of said silicon substrate;

(e) planarizing said substrate;

(f) depositing resist on said substrate and exposing said resist to electromagnetic radiation to pattern said wafer for source and drain contacts and for said gate region; and

(g) etching said oxide layer to form said source and drain contact holes and gate openings while maintaining intact said first poly layer and said oxide liner in the vicinity of said intersection.

2. The method of claim 1 including, after the steps of claim 1, the steps of:

(h) depositing a second resist layer on said substrate and exposing said resist to electromagnetic radiation to pattern said gate mask; and

(i) etching to form a gate opening to remove said polysilicon layer in said gate region while maintaining intact said first poly layer and said oxide liner in the vicinity of said intersection, said gate opening having sidewalls.

3. The method of claim 2 including, after the steps of claim 2, the steps of

(j) thermally growing an oxide spacer on said gate opening sidewalls;

(k) depositing an isolation layer on said thermally grown oxide spacer; and

(1) anisotropically etching said isolation layers while maintaining intact said first poly layer and said oxide liner in the vicinity of said intersection.

4. The method of claim 3 including, after the steps of claim 3, the steps of:

(m) thermally growing a gate oxide layer;

(n) depositing a second poly layer overtop said substrate;

(o) depositing a resist on said substrate exposing said resist with electromagnetic energy and patterning for said source and drain contact mask;

(p) etching said second poly layer through said source and drain contact mask and stopping said etching upon reaching said first poly layer while maintaining intact said first poly layer and said oxide liner in the vicinity of said intersection; and

(q) depositing a third poly layer overtop said wafer.

5. A method for making a short channel metal-oxide semiconductor device in a semiconductor substrate separated from neighboring devices wherein trenches are formed in said substrate to define each device, said trenches having sidewalls lined with an oxide liner and filled with an oxide filler, wherein said device includes lightly doped source and drain regions and heavily doped source and drain regions having a first conductivity separated by a gate region;

a shallow channel doping region having a second conductivity opposite to said first conductivity formed in said gate region;

a gate oxide formed over said gate region;

a gate electrode comprising doped polysilicon of said first conductivity, said gate electrode having a horizontal and vertical portions, said horizontal portion contacting said gate oxide and said vertical portions extending from said horizontal portion; and

doped polysilicon source and drain contacts, said polysilicon source and drain contacts separated from each of said horizontal portion of said gate electrode by oxide regions;

the improvement comprising;

(a) depositing doped polysilicon layers atop and in contact with said source and drain regions, said polysilicon layers extending beneath said oxide regions and said doped polysilicon source and drain contacts and abutting said oxide liner, said doped polysilicon layers preventing said oxide filler from being overetched to the point of exposing said trench sidewalls during subsequent process steps, thereby preventing the formation of parasitic devices in said sidewalls; and

(b) depositing vertical insulation spacers to separate said gate electrode from said oxide regions, wherein said improvement increases the drive currents attainable by said device.

6. The method of claim 5 further including forming a deep implant of the same conductivity as said shallow channel doping region and contacting said source and drain regions.

7. The method of claim 5 wherein said vertical insulation spacers comprise a nitride.

8. The method of claim 5 wherein said vertical insulation spacers have a thickness ranging from about 300 to 1,000 Å

.

9. The method of claim 5 wherein prior to depositing said vertical insulation spacers, a gate opening is formed through said oxide region and through said doped polysilicon layer to expose a portion of said substrate, whereupon a thin oxide layer is formed on the walls of said gate opening, said thin oxide layer coveting both said oxide region and said doped polysilicon layer defining said opening, and said vertical insulation spacers are formed on said thin oxide.

10. The method of claim 5 wherein the portion of said doped polysilicon layers in contact with said lightly doped source and drain regions is doped to a concentration ranging from about 1×

10¹⁸ to 1×

10¹⁹ cm^-3.

11. The method of claim 5 wherein said shallow channel doping region is self-aligned to said gate oxide and to said lightly doped source and drain regions.

12. The method of claim 5 wherein said lightly doped source and drain regions are doped to a concentration ranging from about 1×

10¹⁸ to 1×

10¹⁹ cm^-3.

13. The method of claim 5 wherein said heavily doped source and drain regions are doped to a concentration ranging from about 1×

10²⁰ to 1×

10²¹ cm^-3.