Method of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack

• US 5,571,754 A
• Filed: 11/09/1995
• Issued: 11/05/1996
• Est. Priority Date: 07/26/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Howell, Wayne J., Kalter, Howard L.
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/555,738
• Time in Patent Office: 362 Days
• Field of Search: 437/208, 437/209, 437/211, 437/214, 437/217, 437/219, 437/220, 437/226
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor

Abstract

An endcap chip is provided for a multichip stack comprising multiple integrated circuit chips laminated together. The endcap chip has a substrate with an upper surface and a edge surface, which extends in a plane orthogonal to the upper surface. At least one conductive, monolithic L-connect is disposed over the substrate such that a first leg extends at least partially over the upper surface of the substrate and a second leg extends at least partially over the edge surface of the substrate. When the endcap chip is located at the end of the multichip stack, the at least one conductive, monolithic L-connect electrically connects metal on an end face of the stack to metal on a side face of the stack. A fabrication process is set forth for producing the endcap chip with lithographically defined dimensions.

Claims

1. A method for forming an endcap chip for use in a multichip stack, said method comprising the steps of:

(a) providing a wafer comprising a substrate having an upper surface and a lower surface;

(b) forming a trench in said wafer, said trench defining in said substrate a substrate edge;

(c) forming a conductive, monolithic L-connect having a first leg extending at least partially over said upper surface of said substrate and a second leg extending at least partially over said substrate edge, said second leg having a substantially planar outer surface;

(d) separating the endcap chip from said wafer at least partially along said trench such that said endcap chip includes said conductive, monolithic L-connect, said second leg of said conductive, monolithic L-connect residing at an edge surface of said endcap chip, wherein when said endcap chip is employed within said multichip stack, said conductive, monolithic L-connect electrically interconnects metal on an end face of said multichip stack and metal on a side face of said multichip stack, said side face being parallel to said edge surface of said endcap chip.

2. The method of claim 1, further comprising forming a conformal insulating layer over said upper surface of said substrate and said substrate edge, and wherein said forming step (c) includes forming said conductive, monolithic L-connect above said conformal insulating layer.

3. The method of claim 1, further comprising prior to said step (d), thinning said substrate from said lower surface towards said trench, said thinning continuing until a bottom of said trench is reached.

4. The method of claim 1, wherein said forming step (b) comprises forming a first set of parallel trenches in said wafer and a second set of parallel trenches in said wafer, said trench comprising one trench of said first set of parallel trenches in said wafer, said first set of parallel trenches being orthogonal to said second set of parallel trenches such that multiple rectangular-shaped endcap chips are defined thereby in said wafer, each endcap chip having four edge surfaces.

5. The method of claim 4, wherein said forming step (c) comprises forming multiple conductive, monolithic L-connects for each endcap chip defined in said wafer.

6. The method of claim 5, wherein at least two conductive, monolithic L-connects of said multiple conductive, monolithic L-connects of each endcap chip have second legs extending over different substrate edges of the endcap chip.

7. The method of claim 1, wherein said separating step (d) includes dicing the endcap chip from the wafer along an edge undefined by said trench.

8. The method of claim 1, wherein said multichip stack includes a first metallization on a side face thereof, said first metallization comprising a first type of metal, and wherein said forming step (c) includes forming the conductive, monolithic L-connect from said first type of metal.

9. The method of claim 1, further in combination with integrating said endcap chip into said multichip stack, said integrating including laminating said endcap chip to an exposed principal surface of an integrated circuit chip in said multichip stack such that said second leg of said conductive, monolithic L-connect resides at the side face of said multichip stack, metallizing said side face of said multichip stack with a first metal such that said first metal directly physically contacts said second leg of said conductive, monolithic L-connect, and metallizing the end face of said multichip stack over said endcap chip with a second metal such that said conductive, monolithic L-connect electrically interconnects said second metal on said end face and said first metal on said side face of said multichip stack.

10. A method for forming a chip for use in a multichip stack, said method comprising the steps of:

(a) providing a wafer comprising a substrate having an upper surface and a lower surface;

(b) forming a trench in said wafer, said trench defining in said substrate a substrate edge;

(c) forming a conductive, monolithic L-connect having a first leg extending at least partially over said upper surface of said substrate and a second leg extending at least partially over said substrate edge, said second leg having a substantially planar outer surface; and

(d) separating the chip from said wafer at least partially along said trench such that said chip includes said conductive, monolithic L-connect, said second leg of said conductive, monolithic L-connect residing at an edge surface of said chip, wherein when said chip is employed within said multichip stack, said conductive, monolithic L-connect electrically connects to metal on a side face of said multichip stack, said side face being parallel to said edge surface of said chip.