Voltage-driven type semiconductor device

• US 5,572,048 A
• Filed: 11/17/1993
• Issued: 11/05/1996
• Est. Priority Date: 11/20/1992
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sugawara, Yoshitaka
• Primary Examiner(s): Crane, Sara W.
• Application Number:
  US08/153,047
• Time in Patent Office: 1,084 Days
• Field of Search: 257/132, 257/139, 257/212, 257/341, 257/378
• US Class Current: 257/132
• CPC Class Codes: H01L 27/0716 in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0722 in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

According to the present invention, a MOSFET is formed of an n source, a p well, an n drain and a MOS gate electrode, a bipolar transistor is formed of an n emitter, a p base and an n collector formed in sequential order adjacent to the n drain. These transistors are formed by being merged with each other by the contact of n drain and the n emitter of the same conductivity type. Holes are injected into the drain of a voltage-driven type transistor comprised of the MOSFET from the bipolar transistor having a very small collector saturation resistance. With this, it is possible to give rise to conductivity modulation in the drain of the MOSFET, while the power dissipation of the voltage-driven type semiconductor device becomes very small.

Claims

1. A voltage-driven type semiconductor device comprising:

a first device having a linear volt-ampere characteristic, said first device including a first semiconductor region of first conductivity type said first device being provided with a first electrode applied with drive voltage at a first surface thereof, and having a pair of main electrodes to provide a predetermined voltage across the first semiconductor region;

a second semiconductor region, distinct from the first device, of a second conductivity type located at a position at a distance from said first surface of said first device and for injecting carriers into said first semiconductor region so as to modulate conductivity thereof;

a second electrode coupled to said second semiconductor region,

wherein said second semiconductor region is formed on a plane opposite to said first surface in said first device

wherein said first device portion is comprised of a voltage-driven type transistor, said first semiconductor region is a drain region of said voltage-driven type transistor, said second semiconductor region is a base of a bipolar transistor, and wherein said first and second semiconductor regions have the opposite conductivity type, and are coupled with each other through an emitter region of said bipolar transistor, and

wherein a third semiconductor region for connecting a collector region and said emitter region with each other is provided in the base region of said bipolar transistor, and said third semiconductor region has the same conductivity type as that of said emitter.

2. A voltage-driven type semiconductor device comprising:

a first semiconductor region of a first conductivity type having a pair of main surfaces;

a second semiconductor region of a second conductivity type coupled with one of said pair of main surfaces of said first semiconductor region;

a third semiconductor region of the first conductivity type coupled with said second semiconductor region;

a fourth semiconductor region of the first conductivity type coupled with the other main surface of said first semiconductor region;

a fifth semiconductor region of the second conductivity type coupled with said fourth semiconductor region;

a sixth semiconductor region of the first conductivity type coupled with said fifth semiconductor region;

a gate electrode arranged on a date insulator over a portion of said second semiconductor region between said first semiconductor region and said third semiconductor region;

a first main electrode contacting with said second semiconductor region and said third semiconductor region; and

a second main electrode contacting with said sixth semiconductor region,

wherein said second semiconductor region and said fifth semiconductor region are buried so as to be exposed on the main surface of said first semiconductor region, said third semiconductor region is buried in said second semiconductor region and said sixth semiconductor region is buried in said fifth semiconductor region.