Hall effect device formed in an epitaxial layer of silicon for sensing magnetic fields parallel to the epitaxial layer

• US 5,572,058 A
• Filed: 07/17/1995
• Issued: 11/05/1996
• Est. Priority Date: 07/17/1995
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Biard, James R.
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/503,167
• Time in Patent Office: 477 Days
• Field of Search: 257/427, 257/421, 257/423, 257/426, 73/Dig. 3, 73/514.31, 73/514.08, 324/207.2, 324/252, 324/251, 338/32 H
• US Class Current: 257/421
• CPC Class Codes: G01R 33/077 Vertical Hall-effect devices
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 MRAM devices H10B61/00
• CPC Class Codes: Y10S 73/03 Hall effect

Abstract

A vertical Hall element is formed within the epitaxial layer of a semiconductor and isolated from other components by a P type isolation diffusion. A position defining diffusion is used to accurately locate a plurality of openings within the position defining diffusion where contact diffusions are made. The position defining diffusion is made simultaneously with the base diffusion for transistors within the integrated circuit and the contact diffusions are made simultaneously with the emitter diffusion of transistors within the integrated circuit. Five contact diffusions are provided on the upper surface of the epitaxial layer and generally aligned within the region defined as the Hall element by the isolation diffusions. The center contact is used to provide electrical current flowing through the Hall effect element. Electrical current is split and flows to the two end contact diffusions. The remaining two contact diffusions are used as sensing contacts and are each placed between the center contact and one of the two end contacts. By using the openings within the base diffusion, the contact diffusions can be accurately located and sized in order to improve the efficiency, sensitivity and accuracy of the vertical Hall element.

Claims

1. An integrated circuit with a vertical Hall element, comprising:

a substrate comprising a material of a first conductivity type;

an epitaxial layer disposed on a first surface of said substrate, said epitaxial layer comprising a material of a second conductivity type;

a transistor base diffusion within said epitaxial layer, said transistor base diffusion having a depth of a first magnitude, said transistor base diffusion comprising a material of said first conductivity type;

a transistor emitter diffusion within said epitaxial layer, said transistor emitter diffusion having a depth of a second magnitude, said second magnitude being less than said first magnitude, said transistor emitter diffusion comprising a material of said second conductivity type;

means for isolating a Hall effect region of said epitaxial layer;

a position defining diffusion comprising a material of said first conductivity type, said position defining diffusion having first, second, third, fourth and fifth openings formed therein, said position defining diffusion being diffused within said epitaxial layer simultaneously with said transistor base diffusion, said first, second, third, fourth and fifth openings being disposed within said Hall effect region;

first, second, third, fourth and fifth contact diffusions comprising a material of said second conductivity type and being diffused within said first, second, third, fourth and fifth openings, respectively, within said epitaxial layer simultaneously with said transistor emitter diffusion, said first, second, third, fourth and fifth contact diffusions being disposed within said Hall effect region;

first means for connecting said third contact diffusion to a first terminal of a power supply circuit;

second means for connecting said first and fifth contact diffusions to a second terminal of said power supply circuit; and

third means for connecting said second and fourth contact diffusions to a means for measuring a voltage differential.

2. The integrated circuit of claim 1, wherein:

said isolating means comprises a diffusion of a material of said first conductivity type extending from a surface of said epitaxial layer to said substrate.

3. The integrated circuit of claim 1, wherein:

said first conductivity type material is P type material and said second conductivity type material is N type material.

4. The integrated circuit of claim 1, wherein:

said first connecting means comprises a metallic layer.

5. The integrated circuit of claim 1, wherein:

said second connecting means comprises a metallic layer.

6. The integrated circuit of claim 1, further comprising:

a buried layer of said second conductivity type diffused into said substrate and said epitaxial layer; and

a sinker diffusion of said second conductivity type extending through said epitaxial layer and into said substrate, said sinker diffusion and said buried layer being disposed in contact with each other.

7. The integrated circuit of claim 1, wherein:

said transistor base diffusion comprises boron.

8. The integrated circuit of claim 1, wherein:

said transistor emitter diffusion comprises phosphorous.

9. The integrated circuit of claim 1, wherein:

the lateral dimensions of said second and fourth contact diffusions are reduced by the diffusion of said position defining diffusion to reduce the size of said second and fourth openings prior to deposition of said second and fourth contact diffusions.

10. An integrated circuit with a vertical Hall element, comprising:

a substrate comprising a material of a first conductivity type;

an epitaxial layer disposed on a first surface of said substrate, said epitaxial layer comprising a material of a second conductivity type;

a transistor base diffusion within said epitaxial layer, said transistor base diffusion having a depth of a first magnitude, said transistor base diffusion comprising a material of said first conductivity type;

a transistor emitter diffusion within said epitaxial layer, said transistor emitter diffusion having a depth of a second magnitude, said second magnitude being less than said first magnitude, said transistor emitter diffusion comprising a material of said second conductivity type;

means for isolating a Hall effect region of said epitaxial layer, said isolating means comprise a diffusion of a material of said first conductivity type extending from a surface of said epitaxial layer to said substrate;

a position defining diffusion comprising a material of said first conductivity type, said position defining diffusion having first, second, third, fourth and fifth openings formed therein, said position defining diffusion being diffused within said epitaxial layer simultaneously with said transistor base diffusion, said first, second, third, fourth and fifth openings being disposed within said Hall effect region;

first, second, third, fourth and fifth contact diffusions comprising a material of said second conductivity type and being diffused within said first, second, third, fourth and fifth openings, respectively, within said epitaxial layer simultaneously with said transistor emitter diffusion, said first, second, third, fourth and fifth contact diffusions being disposed within said Hall effect region;

first means for connecting said third contact diffusion to a source of power;

second means for connecting said first and fifth contact diffusions to a point of ground potential; and

third means for connecting said second and fourth contact diffusions to a means for measuring a voltage differential.

11. The integrated circuit of claim 10, wherein:

said first conductivity type material is P-type material.

12. The integrated circuit of claim 10, wherein:

said second conductivity type material is N-type material.

13. The integrated circuit of claim 10, wherein:

said first connecting means comprises a metallic layer.

14. The integrated circuit of claim 10, wherein:

said second connecting means comprises a metallic layer.

15. The integrated circuit of claim 10, further comprising:

a buried layer of said second conductivity type diffused into said substrate and said epitaxial layer; and

a sinker diffusion of said second conductivity type extending through said epitaxial layer and into said substrate, said sinker diffusion and said buried layer being disposed in contact with each other.

16. The integrated circuit of claim 10, wherein:

said transistor base diffusion comprises boron.

17. The integrated circuit of claim 10, wherein:

said transistor emitter diffusion comprises arsenic.

18. The integrated circuit of claim 10, wherein:

the lateral dimensions of said second and fourth contact diffusions are reduced by the diffusion of said position defining diffusion to reduce the size of said second and fourth openings prior to deposition of said second and fourth contact diffusions.

19. An integrated circuit with a vertical Hall element, comprising:

a substrate comprising a material of a first conductivity type;

an epitaxial layer disposed on a first surface of said substrate, said epitaxial layer comprising a material of a second conductivity type;

a transistor base diffusion within said epitaxial layer, said transistor base diffusion having a depth of a first magnitude, said transistor base diffusion comprising a material of said first conductivity type;

a transistor emitter diffusion within said epitaxial layer, said transistor emitter diffusion having a depth of a second magnitude, said second magnitude being less than said first magnitude, said transistor emitter diffusion comprising a material of said second conductivity type;

means for isolating a Hall effect region of said epitaxial layer, said isolating means comprise a diffusion of a material of said first conductivity type extending from a surface of said epitaxial layer to said substrate;

a position defining diffusion comprising a material of said first conductivity type, said position defining diffusion having first, second, third, fourth and fifth openings formed therein, said position defining diffusion being diffused within said epitaxial layer simultaneously with said transistor base diffusion, said first, second, third, fourth and fifth openings being disposed within said Hall effect region;

first, second, third, fourth and fifth contact diffusions comprising a material of said second conductivity type and being diffused within said first, second, third, fourth and fifth openings, respectively, within said epitaxial layer simultaneously with said transistor emitter diffusion, said first, second, third, fourth and fifth contact diffusions being disposed within said Hall effect region, the lateral dimensions of said second and fourth contact diffusions being reduced by the diffusion of said position defining diffusion to reduce the size of said second and fourth openings prior to deposition of said second and fourth contact diffusions;

first means for connecting said third contact diffusion to a source of power, said first connecting means comprising a metallic layer;

second means for connecting said first and fifth contact diffusions to a point of ground potential, said second connecting means comprises a metallic layer; and

third means for connecting said second and fourth contact diffusions to a means for measuring a voltage differential.

20. The integrated circuit of claim 19, wherein:

said first conductivity type material is P type material and said second conductivity type material is N type material, said transistor base diffusion comprising boron, said transistor emitter diffusion comprising a material selected from a group comprising arsenic and phosphorous.