Voltage-controlled delay element with programmable delay

• US 5,572,159 A
• Filed: 11/14/1994
• Issued: 11/05/1996
• Est. Priority Date: 11/14/1994
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Nexgen Incorporated (Advanced Micro Devices, Inc.)
• Inventors: McFarland, Harold L.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Shin, Eunja
• Application Number:
  US08/339,328
• Time in Patent Office: 722 Days
• Field of Search: 327/530, 327/393, 327/394, 327/396, 327/270, 327/276, 327/281, 327/278, 327/101, 327/103, 327/261, 327/538, 327/541, 330/288, 330/310, 323/315
• US Class Current: 327/276
• CPC Class Codes: G05F 1/466 Sources with reduced influence on propagation delay
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: H03K 2005/00202 using current mirrors
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A voltage-controlled delay element utilizes a current-starved inverter configuration with a feedback path that ensures a rapid discharge of the storage node to ground once the desired delay time has elapsed. The circuit comprises a circuit path for charging the storage node (preferably rapidly), a first pull-down path capable of discharging the storage node at a rate determined by the control voltage, a second pull-down path capable of rapidly discharging the storage node, an output inverter, and a feedback connection between the output terminal of the output inverter and the second pull-down path to rapidly discharge the storage node when the output voltage starts rising. The circuit further comprises a means for programmably adjusting the delay in response to logic signals.

Claims

1. A programmable delay element comprising:

a voltage controlled delay element having a delay period proportional to an analog control voltage;

control voltage determining means connected to said voltages controlled delay element for determining said analog control voltage; and

a plurality of programmable control voltage adjusting means connected to said control voltage determining means for modifying said analog control voltage in response to logic signals, wherein said control voltage determining means comprises;

a source path that sets a base current;

a control voltage generating path connected to said source path that determines said analog control voltage by running a source current that is proportional to said base current over a transistor; and

a gate path connected to said control voltage generating path for draining source current from said control voltage generating path and thereby adjusting said control voltage.

3. The programmable delay element according to claim 1 wherein each of said programmable control voltage adjusting means comprises:

a source path for receiving input signals from the control voltage determining means and for setting a base current;

a switching path coupled to said programmable control voltage source path for switching the programmable control voltage adjusting means on or off in response to one of said logic signals; and

current sinking means connected to said gate path for draining a specified amount of current from said control voltage generating means when said programmable control voltage adjusting means is turned on.

2. A programmable delay element comprising:

a voltage controlled delay element (VCDE);

control voltage determining means connected to said VCDE for determining a control voltage; and

a plurality of programmable control voltage adjusting means for modifying said control voltage in response to logic signals;

wherein said control voltage determining means comprises;

a first source path that sets a base current;

a control voltage generating path connected to said first source path for determining said control voltage by running a source current that is proportional to said base current over a transistor;

a gate path connected to said control voltage generating path for draining source current from said control voltage generating path and thereby adjusting said control voltage;

wherein each of said programmable control voltage adjusting means comprises;

an additional source path for receiving input signals from the control voltage determining means to set a second base current;

a switching path coupled between said additional source path and a current sinking means for switching the programmable control voltage adjusting means on or off in response to one of said logic signals by connecting or not connecting said additional source path to said current sinking means; and

wherein said current sinking means connected to said gate path drains a specified amount of current from said control voltage generating means when connected to said additional source path.

4. A programmable delay element comprising:

a circuit capable of producing an output signal that follows an input signal with a delay that is proportional to a control signal applied at a control signal input;

a control signal determining circuit with an output operably connected to said control signal input and a load input; and

a plurality of programmable control signal adjusting circuits operably connected to said load input for modifying said control signal in response to logic signals wherein said control signal determining circuit comprises;

a source path that sets a base current;

a control signal generating path connected to said source path that determines said control signal by running a source current that is proportional to said base current over a transistor; and

a gate path connected to said control signal generating path for draining source current from said control signal generating path and thereby adjusting said control signal.

5. The programmable delay element according to claim 4 wherein each of said programmable control signal adjusting circuits comprises:

a source path for receiving input signals from the control signal determining circuit to set a base current;

a switching path to switch the programmable control signal adjusting means on or off in response to one of said logic signals; and

a current sink connected to said gate path that drains a specified amount of current from said control signal determining circuit when said programmable control signal adjusting means is turned on.

6. A programmable delay element comprising:

a circuit capable of producing an output signal that follows an input signal with a delay that is a function of a control signal applied at a control input;

a base-mirror circuit with an output operably connected to said control input and a gate input; and

a plurality of gate-mirror circuits operably connected to said base-mirror circuit via said gate input;

wherein said base-mirror circuit comprises;

a first source half of a first current-mirror circuit, said first source half having external reference signal inputs;

a second current-mirror circuit comprising a second reference half operably connected to said first source half and a second source half;

a third reference half of a third current-mirror circuit operably connected to said second source half, said third reference half connectable to a third source half in a gate-mirror circuit; and

a gate path connected to said second source half for draining source current from said second source half.

7. The programmable delay element according to claim 6 wherein at least one of said gate-mirror circuits comprises:

said third source half of said third current-mirror circuit, said third source half connected to said third reference half, said third source half connected to the gate path for draining a specified amount of current from said second source half when said gate mirror is turned on; and

a switch transistor to switch said gate mirror on or off in response to a logic signal.

8. The programmable delay element according to claim 6 wherein each of said plurality of gate-mirror circuits comprises:

said third source half of said third current-mirror circuit, said third source half connectable to said third reference half, said third source half connected to the gate path for draining a specified amount of current from said second source half when said gate mirror is turned on, said specified amount of current depending on a number of transistors in parallel in said third source half wherein at least one of said gate-mirror circuits has a third source half with a different number of transistors in parallel than another of said gate-mirror circuits; and

a switch transistor to switch said third source half on or off in response to a logic signal.

9. The programmable delay element according to claim 8 wherein said base-mirror circuit generates a current signal I_X used to determine the delay of said delay element, said current signal I_X represented by the equation:

space="preserve" listing-type="equation">I.sub.X =[K.sub.2 /(1+K.sub.5 (Na+Mb+Lc))]*I.sub.PWINT

where I_PWINT is a current that is externally generated, K₂ and K₅ are constants determined by the size of the transistors within said base-mirror and said gate-mirror circuits, a, b and c are either 0 or 1 depending whether their respective gate-mirrors are on or off, and L, M, and N are constants representing the number of transistors in parallel in each gate mirror.

10. The programmable delay element according to claim 8 wherein said base-mirror circuit generates a current signal I_X used to modify the delay of said delay element, said current signal I_X represented by the equation:

space="preserve" listing-type="equation">I.sub.X =[K.sub.2 /(1+K.sub.5 *ε

N.sub.n a.sub.n)]*I.sub.PWINT

where I_PWINT is a current that is externally generated, K₂ and K₅ are constants determined by the size of the transistors within said base-mirror and said gate-mirror circuits, and the expression ε

N_n a_n represents the sum of the current drained by each gate-mirror circuit n, having a number of transistors in parallel N_n and multiplied by its respective binary on/off value a_n.

11. The programmable delay element according to claim 6 wherein said delay (T) is represented by the equation

12. The programmable delay element according to claim 6 wherein said delay (T) is represented by the equation