Frequency synthesizer having dual phase locked loops

• US 5,572,168 A
• Filed: 08/09/1995
• Issued: 11/05/1996
• Est. Priority Date: 08/09/1995
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Kasturia, Sanjay
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/513,195
• Time in Patent Office: 454 Days
• Field of Search: 331/1 A, 331/2, 331/16, 331/17, 331/18, 331/25, 327/105, 327/107, 327/147-150, 327/156-159, 455/260
• US Class Current: 331/2
• CPC Class Codes: H03K 23/66 with a variable counting base, e.g. by presetting or by adding or suppressing pulses
• CPC Class Codes: H03K 23/667 by switching the base during a counting cycle
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03K 3/03 Astable circuits
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A frequency synthesizer circuit for the front end of an RF system. The frequency synthesizer uses two pulse-swallow phase-locked loops in a synthesizer architecture that produces an output frequency that is a function of the two reference frequencies used as inputs into the two phase-locked loops. As a result, the frequency synthesizer can be incremented in steps equal to the differential of the reference frequencies of the two phase-locked loops, while the frequency outputs of each of the phase-locked loops can be incremented in much larger steps. This enables the two phase-locked loops to employ relatively large bandwidths, thereby achieving a faster signal lock as well as a better suppression of the voltage controlled oscillator (VCO) phase noise in each loop. The use of a dual loop synthesizer architecture allows for feedback correction of the VCO phase noise outside the loop bandwidth.

Claims

1. A frequency synthesizer capable of selectively switching between an initial frequency and a subsequent frequency separated by an incremental difference, comprising:

a first phase-locked loop wherein said first phase-locked loop receives a first reference frequency and produces a first output frequency that is a function of said first reference frequency;

a second phase-locked loop wherein said second phase-locked loop receives a second reference frequency and provides a second output frequency that is a function of said second reference frequency; and

a mixer for mixing said first output frequency and said second output frequency to produce said subsequent frequency, wherein said subsequent frequency is a function of both said first reference frequency and said second reference frequency, and said incremental difference between said initial frequency and said subsequent frequency is equal to a difference between said first reference frequency and said second reference frequency.

2. The frequency synthesizer according to claim 1 further including a high pass filter coupled to said mixer for filtering said subsequent frequency.

3. The frequency synthesizer according to claim 1 wherein said first phase-locked loop and said second phase-locked loop both include a voltage controlled oscillator, a prescaler, a swallow counter and a program counter.

4. The frequency synthesizer according to claim 3 wherein said program counter in said first phase-locked loop includes a first value divider circuit and said program counter in said second phase-locked loop includes a second value divider circuit, wherein first value divider circuit and said second value divider circuit are not equivalent.

5. The frequency synthesizer according to claim 4 wherein said first value divider circuit is a ÷

20 circuit and said second value divider circuit is a ÷

30 circuit.

6. The frequency synthesizer according to claim 3 wherein each said program counter includes at least one synchronous divider and at least one asynchronous divider circuit, wherein said synchronous divider circuit produces a reset signal read by said pulse swallow circuit.

7. The frequency synthesizer according to claim 3 wherein said voltage controlled oscillator is a four stage ring oscillator.

8. The frequency synthesizer according to claim 7 wherein each stage in said four stage ring oscillator produces at least one signal that is 180 degrees out of phase with another signal produced by said four stage oscillator so as to produce first order cancellation.

9. The frequency synthesizer according to claim 7 wherein each stage of said four stage ring oscillator includes an NMOS transistor differential pair that are biased at a tail current of approximately 0.75 mA.

10. The frequency synthesizer according to claim 7 wherein said voltage controlled oscillator further includes a positive/negative feedback circuit, wherein as a feedback from said positive/negative feedback circuit goes from positive to negative the impedance associated with each port of said voltage controlled oscillator decreases, thereby increasing oscillation rate.

11. The frequency synthesizer according to claim 1, wherein said first phase-locked loop produces said first output frequency and said second phase-locked loop produces said second output frequency, simultaneously.

12. The frequency synthesizer according to claim 1, wherein a first incremental difference exists between said first reference frequency and said first output frequency, and a second incremental difference exists between said second reference frequency and said second output frequency, wherein said first incremental difference is not equal to said second incremental difference.

13. A frequency synthesizer capable of selectively switching between an initial frequency and a subsequent frequency separated by a multiple of a base incremental difference, comprising;

a first phase-lock loop that receives a first reference frequency;

at least one second phase-lock loop that receives a second reference frequency; and

a mixer for mixing the output associated with said first phase-locked loop and said second phase-locked loop to produce said subsequent frequency, wherein said base incremental difference is equal to a difference between said first reference frequency and said second reference frequency.

14. The frequency synthesizer according to claim 13, wherein said first phase-locked loop and said at least one second phase-locked loop each includes a voltage controlled oscillator and a feedback loop that includes a dual modulus prescaler, a program counter and a pulse swallow counter, arranged as a pulse swallow.

15. The frequency synthesizer according to claim 14 wherein said voltage controlled oscillator is a four stage ring oscillator.

16. The frequency synthesizer according to claim 13 wherein said frequency synthesizer receives input frequency (f0) and said frequency synthesizer produces said subsequent frequency (fout) wherein fout=2f0÷

k(fref1-fref2). k is a value that is dependent upon the number of signal channels, fref1 is said first reference frequency and fref2 is said second reference frequency.

17. The frequency synthesizer according to claim 15, wherein said voltage controlled oscillator further includes a means for providing positive and negative feedback, wherein the impedance at each port associated with the voltage controlled oscillator decreases as the feedback changes from positive to negative.

18. The frequency synthesizer according to claim 14 wherein said program counter in said first phase-locked loop includes a first value divider circuit and each said program counter in said at least one phase-locked loop includes a second value divider, wherein said first value divider circuit and each said second value divider circuit are not equivalent.

19. The frequency synthesizer according to claim 15 wherein each stage of said four stage ring oscillator includes a differential pair of NMOS transistors with PMOS loads.

20. The frequency synthesizer according to claim 17 wherein said means for producing positive and negative feedback include the use of a plurality of differential transistor pairs within said voltage controlled oscillator.

21. The frequency synthesizer according to claim 14 wherein said voltage controlled oscillator and said dual modulus prescaler are differential circuits.

22. The frequency synthesizer according to claim 14 wherein said dual modulus prescaler divides an input frequency by a predetermined number (N) when said input frequency has a high modulus, and divides said input frequency by said predetermined number minus one (N-1) when said input frequency has a low modulus.

23. The frequency synthesizer according to claim 13, wherein said first phase-locked loop produces said first output frequency and said second phase-locked loop produces said second output frequency, simultaneously.

24. The frequency synthesizer according to claim 13, wherein a first incremental difference exists between said first reference frequency and said first output frequency, and a second incremental difference exists between said second reference frequency and said second output frequency, wherein said first incremental difference is not equal to said second incremental difference.