Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models

• US 5,572,437 A
• Filed: 05/20/1994
• Issued: 11/05/1996
• Est. Priority Date: 04/06/1990
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Bair, Owen S., Dangelo, Carlos, Rostoker, Michael D.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/246,798
• Time in Patent Office: 900 Days
• Field of Search: 364/488, 364/489, 364/490, 364/578, 395/500
• US Class Current: 716/105
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

An automatic logic-model generation system operates on a behavioral description of an electronic design (e.g., a circuit, a system, etc.) to automatically generate a low-level (i.e., circuit-level) design of the electronic design, to lay out the electronic design for production in the form of an integrated circuit, and to produce logic-level models incorporating accurate timing (and delay) information. A verification process is also performed whereby the logic-level model is automatically verified for accuracy.

Claims

1. A method of verifying a logic model of an electronic design, in an ECAD system, comprising:

providing a logic-level model of the electronic design;

obtaining timing and delay information obtained from a transistor-level model simulation of the design; and

providing the timing and delay information to the logic-level model for simulation.

2. A method of creating and validating a structural description of an electronic design from a behavioral description thereof, comprising:

providing a behavioral description of the electronic design;

simulating and changing the behavioral description of the design;

partitioning the behavioral description into a number of architectural blocks and constraining the architectural choices to those which meet high-level timing goals; and

synthesizing the architectural blocks into a structural description of the design.

3. A method of creating an electronic design on an ECAD system, comprising:

synthesizing a physical description of the electronic design from a behavioral description of the electronic system;

generating an interim logic-level model representation of the design; and

simulating the logic-level model representation of the electronic system using information derived from the physical description of the design.

4. A method of designing an electronic system on an ECAD system, comprising:

synthesizing a physical description of the electronic system from a behavioral description of the electronic system, generating an interim logic-level model representation of the electronic system; and

simulating the logic-level model representation of the electronic system using information derived from the physical description of the electronic system.

5. An electronic design system comprising:

means for creating a net-list description of an electronic design from a behavioral description of the design;

means for analyzing the behavioral description for input-to-output dependencies corresponding to logical relationships between inputs and outputs of said design and for creating a list of the input-to-output dependencies;

means for determining input patterns and corresponding output transitions, according to said input-to-output dependencies, and for creating a list of the input patterns;

means for performing a circuit-level simulation of the design according to said lists of input-to-output dependencies and input patterns;

means for extracting delay and timing information from the circuit-level simulation of the design;

means for performing a gate-level simulation of the design, using the extracted delay and timing information, and for creating a logic-level model the design; and

means for simulating the logic-level model of the design.

6. An electronic design system, according to claim 5, further comprising:

means for simulating a switch-level representation of the design; and

means for comparing the switch-level and logic-level simulations.

7. An electronic design system, according to claim 5, further comprising:

means for providing information from the simulated logic-level model of the design in human-readable form in the form of a data sheet.

8. An electronic design system, according to claim 5, further comprising:

means for combining the timing information into the logic-level model to produce a single multi-mode logic model of the design.

9. An electronic design system, according to claim 5, further comprising:

means for automatically generating a translated test pattern file;

means for automatically generating a multi-mode file;

means for running a comparison simulation using the test pattern file and the multi-mode file; and

means for comparing the results of the circuit-level simulation with the comparison simulation.

10. An automatic logic model generation system comprising:

means for operating on inputs and storing a net-list representation of an electronic design;

means for simulating performance of a logic-level model of the design as interconnected logic blocks;

means for simulating performance of a transistor-level model of the design;

means for providing layout information to the transistor-level model of the design;

means for providing timing and delay information obtained from the simulated performance of the transistor-level model to the logic blocks; and

means for synthesizing a physical description of the electronic system from a behavioral description of the electronic system.

12. An automatic model generation system, according to claim 10, further comprising:

means for providing timing and delay information obtained for the transistor-level simulation to the switch-level model.

13. An automatic model generation system, according to claim 10, further comprising:

means for providing said logic-level model in a human-readable data-sheet form.

17. An automatic model generation system, according to claim 13, further comprising:

providing said logic-level model in a human-readable data-sheet form.

11. An automatic model generation system, according to claim further comprising:

means for simulating a switch-level representation of the design;

means for comparing the logic-level simulation with the switch-level simulation, according to pre-determined criteria for success; and

means for providing an indication of a result of said comparison.

14. Method of generating logic and timing models in an ECAD system, comprising:

operating on inputs and storing a net-list representation of an electronic design;

simulating performance of a logic-level model of the design as interconnected logic blocks;

simulating performance of a transistor-level model of the design;

providing layout information to the transistor-level model of the design;

providing timing and delay information obtained from the simulated performance of the transistor-level model to the logic blocks; and

synthesizing a physical description of the electronic system from a behavioral description of the electronic system.

15. An automatic model generation system, according to claim 14 further comprising:

simulating a switch-level representation of the design;

comparing the logic-level simulation with the switch-level simulation, according to pre-determined criteria for success; and

providing an indication of a result of said comparison.

16. An automatic model generation system, according to claim 14, further comprising:

providing timing and delay information obtained for the transistor-level simulation to the switch-level model.