Block architected static RAM configurable for different word widths and associated method for forming a physical layout of the static RAM
First Claim
1. A method for clocking a block architected SRAM having block decode circuitry and row decode circuitry for respectively enabling a memory block of a plurality of memory blocks and a row of the memory block, the method comprising the steps of:
- providing a first clock signal for synchronously starting a decode sequence;
initializing control signals of the block decode circuitry to enable each memory block of said plurality of memory blocks;
initializing control signals of the row decode circuitry to enable each memory row of each memory block;
providing an address corresponding to a memory word in the memory block to the block decode circuitry and the row decode circuitry when said first clock signal transitions to a first phase; and
preventing memory words of each memory block from being accessed with a second clock signal, said second clock signal is delayed from said first clock signal.
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Accused Products
Abstract
A method for building a compilable static RAM (SRAM). A central block structure (54) is formed which includes clock buffers (28), a delayed clock buffer (29), row address buffers (27), row deselect circuits (21), row driver circuits (22), output level translators, and a databus interface. A memory block macro (35) is built which includes a block of memory, precharge circuits, multiplexers, read/write multiplexers, and sense amplifiers. If multiple memory blocks are used a block deselect circuit (39) and row/block decoders (38) must be added to the memory block macro (35). A row and block deselection process is used in the SRAM architecture to simplify compilability and enhance speed.
25 Citations
15 Claims
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1. A method for clocking a block architected SRAM having block decode circuitry and row decode circuitry for respectively enabling a memory block of a plurality of memory blocks and a row of the memory block, the method comprising the steps of:
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providing a first clock signal for synchronously starting a decode sequence; initializing control signals of the block decode circuitry to enable each memory block of said plurality of memory blocks; initializing control signals of the row decode circuitry to enable each memory row of each memory block; providing an address corresponding to a memory word in the memory block to the block decode circuitry and the row decode circuitry when said first clock signal transitions to a first phase; and preventing memory words of each memory block from being accessed with a second clock signal, said second clock signal is delayed from said first clock signal. - View Dependent Claims (2, 3, 4, 5)
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6. A method of docking a block architected SRAM having block decode circuitry and row decode circuitry for respectively enabling a memory block of a plurality of memory blocks and a row of the memory block, the method comprising the steps of:
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providing a first clock signal for synchronously starting a decode sequence; providing an address corresponding to a memory word in the memory block to the block decode circuitry and the row decode circuitry when said first clock signal transitions to a first phase; and preventing said memory word from being accessed with a second clock signal, said second clock signal is delayed from said first clock signal. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A method for clocking a Static Random Access Memory (SRAM) comprising the steps of:
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providing a clock signal for synchronously starting a decode sequence; and delaying a second clock signal for a predetermined time period for disabling circuitry of the SRAM from accessing memory locations for said predetermined time. - View Dependent Claims (13, 14, 15)
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Specification