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Block architected static RAM configurable for different word widths and associated method for forming a physical layout of the static RAM

  • US 5,572,482 A
  • Filed: 06/12/1995
  • Issued: 11/05/1996
  • Est. Priority Date: 11/28/1994
  • Status: Expired due to Fees
First Claim
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1. A method for clocking a block architected SRAM having block decode circuitry and row decode circuitry for respectively enabling a memory block of a plurality of memory blocks and a row of the memory block, the method comprising the steps of:

  • providing a first clock signal for synchronously starting a decode sequence;

    initializing control signals of the block decode circuitry to enable each memory block of said plurality of memory blocks;

    initializing control signals of the row decode circuitry to enable each memory row of each memory block;

    providing an address corresponding to a memory word in the memory block to the block decode circuitry and the row decode circuitry when said first clock signal transitions to a first phase; and

    preventing memory words of each memory block from being accessed with a second clock signal, said second clock signal is delayed from said first clock signal.

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