Network interface

• US 5,572,658 A
• Filed: 02/27/1995
• Issued: 11/05/1996
• Est. Priority Date: 09/02/1992
• Status: Expired due to Term

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Schmiederer, Claus, Mohr, Thomas, Kern, Robert, Decker, Gerhard
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US08/392,924
• Time in Patent Office: 617 Days
• Field of Search: 371/29.5, 371/11.2, 371/8.2, 370/16, 370/43, 370/85.1, 318/618, 56/10.2 H, 364/431.04, 364/424.01
• US Class Current: 714/4.5
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 2012/40215 Controller Area Network CAN
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle

Abstract

A network interface is designed for two-wire reception via a serial bus and has a differential receiver which is connected to input lines. The network interface likewise has an element for recognizing error states on the bus lines. It is designed such that it changes into single-wire operation after recognizing the error state, in order to maintain the data traffic. In this case, one input line is connected to a fixed terminal potential. The terminal potential is in this case selected such that the magnitude of the potential difference between the two input lines is the same for both bit levels.

Claims

1. A network interface of a serial bus having at least a first bus line and a second bus line, comprising a differential receiver;

at least a first input line and a second input line to which said differential receiver is connected, each of said input lines being connected to one of the bus lines;

means for recognizing error states in a digital transmission of data via the bus;

first further means which set a magnitude of a voltage difference between said two input lines (RX0, RX1) during error-free operation to a different magnitude for both bit levels;

second further means which set said first input line (RX1) to a first terminal potential UK0 in accordance with the formula;

space="preserve" listing-type="equation">UK0=(U.sub.RX1 (dom)+U.sub.RX1 (rec))/2

if the bus line connected to said first input line (RX1) is in an error state, said second further means setting said second input line (RX0) to a second terminal potential UK1 in accordance with the formula;

space="preserve" listing-type="equation">UK1=(U.sub.RX0 (dom)+U.sub.RX0 (rec))/2

if the bus line connected to said second input line (RX0) is in an error state, said first and second terminal potentials being different from each other such that U_RX1 (dom) and U_RX1 (rec) represent a respective input potential for one of the two bit levels on said first input line, and U_RX0 (dom) and U_RX0 (rec) represent a respective input potential for one of the two bit levels on said second input line.

2. A network interface as defined in claim 1, wherein said means for recognizing error states in the digital transmission of data via the bus is means for recognizing short circuit in the bus lines.

3. A network interface as defined in claim 1, wherein said means for recognizing error states in the digital transmission of data via the bus is means for recognizing interruption states in the bus lines.

4. A network interface as defined in claim 1;

and further comprising a plurality of points of a resistor network; and

means for reproducing a reception of data via the bus and including two controllable switches connecting respectively at least one of said input lines to one bus line in a first switching state, and connecting at least one of said input lines to a respective one of said points of said resistor network in a second switching state.

5. A network interface as defined in claim 4, wherein said switches include a first switch connecting said first input line to a first one of said points of said resistor network, while said second switch connects said second input line to a second one of said points of said resistor network, said first point and said second point being different points of said resistor network.

6. A network interface as defined in claim 4, wherein said resistor network is formed so that a recessive bit level is present on said input lines when both said switches have been moved into the second switching state.

7. A network interface as defined in claim 1;

and further comprising a bus coupling network connected between said input lines and the bus lines.

8. A network interface as defined in claim 7, wherein said bus coupling network includes two input voltage dividers connectable to the at least two bus lines.