System and method for obtaining correct byte addresses by using logical operations on 2 least significant bits of byte address to facilitate compatibility between computer architectures having different memory orders

• US 5,572,713 A
• Filed: 01/27/1995
• Issued: 11/05/1996
• Est. Priority Date: 08/09/1990
• Status: Expired due to Term

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Himelstein, Mark I., Weber, Larry B., Killian, Earl A.
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US08/379,710
• Time in Patent Office: 648 Days
• Field of Search: 395/500
• US Class Current: 703/27
• CPC Class Codes: G06F 7/768 Data position reversal, e.g. bit reversal, byte swapping
• CPC Class Codes: G06F 9/34 Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes address translation G06F12/00

Abstract

A method and computer program-product for converting a program designed to be executed on a computer system employing a first predefined memory order, such as the Big Endian architecture, to a program which is executable on a computer system employing a second predefined memory order, such as the Little Endian architecture. The method and computer program-product uses the fact that performing a logical operation on the lower two bits of a byte address in one architecture converts that byte address to the equivalent byte address in the other architecture. The method and computer program-product are implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and operating on the two least significant bits of the byte address with a logical operation to generate two complementary bits used to replace the two least significant bits of the byte address to generate a new byte address that corresponds with the other architecture.

Claims

1. A method for converting a program designed to be executed on a computer system employing a first predefined memory order to a program which is executable on a computer system employing a second predefined memory order different from said first predefined memory order, the method comprising the steps of:

finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits;

operating on the two least significant bits of each byte address using a logic function to thereby generate two complementary bits for each byte address; and

replacing the two least significant bits of the byte address with two complementary bits to thereby generate a new byte address for each of said bytes of data.

2. The method of claim 1 further comprising the step of detecting whether the program is designed to be executed on a computer system employing the first predefined memory order.

3. The method of claim 2 further comprising the step of detecting the two least significant bits of each byte address.

4. The method of claim 1 wherein the first predefined memory order comprises big endian order and the second predefined memory order comprises little endian order.

5. A computer system employing a first predefined memory order which converts and executes programs designed to be executed on computer systems employing a second predefined memory order different from said first predefined memory order, comprising:

means for finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits;

means for operating on the least two significant bits of each byte address using a logic function to thereby generate two complementary bits for each byte address; and

means for replacing the least two significant bits of each byte address with the two complementary bits to thereby generate a new byte address for each of said bytes of data.

6. The computer system of claim 5 further comprising:

means for detecting whether the program is designed to be executed on a computer system employing the first predefined memory order; and

means for detecting the two least significant bits of each byte address.

7. The computer system of claim 5 wherein the first predefined memory order comprises big endian order and the second predefined memory order comprises little endian order.

8. A computer program-product storage device readable by a computer system, tangibly embodying a computer program-product comprising instructions executable by the computer system to perform method steps for converting a program designed to be executed on a computer system employing a first predefined memory order to a program which is executable on a computer system employing a second predefined memory different from said first predefined memory order, the method comprising the steps of:

finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits;

operating on the two least significant bits of each byte address using a logic function to thereby generate two complementary bits for each byte address; and

replacing the two least significant bits of the byte address with two complementary bits to thereby generate a new byte address for each of said bytes of data.

9. The computer program-product storage device of claim 8, wherein said method further comprises the step of detecting whether the program is designed to be executed on a computer system employing the first predefined memory order.

10. The computer program-product storage device of claim 8, wherein said method further comprises the step of detecting the two least significant bits of each byte address.

11. The computer program-product storage device of claim 8, wherein the first predefined memory order comprises big endian order and the second predefined memory order comprises little endian order.