Method and apparatus for assigning and analyzing timing specifications in a computer aided engineering program

• US 5,572,717 A
• Filed: 04/06/1994
• Issued: 11/05/1996
• Est. Priority Date: 04/06/1994
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Pedersen, Bruce
• Primary Examiner(s): Kriess, Kevin A.
• Assistant Examiner(s): Banankhah, Majid A.
• Application Number:
  US08/223,914
• Time in Patent Office: 944 Days
• Field of Search: 395/550, 364/490, 364/491
• US Class Current: 713/500
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A system for allowing a user to assign timing specifications to points in a circuit and have the timing properties of the circuit analyzed with respect to the timing specifications. The system allows timing specifications such as maximum propagation delay, clock-to-output delay, setup time and maximum clock frequency to be assigned at any point in the circuit. The system uses predefined rules to determine which of multiple possible specifications are to be used in analyzing each path of the circuit. A method of concurrently performing the assignment and analysis is described.

Claims

1. A method for applying timing specifications in a logic design, wherein the logic design includes logic design inputs, logic design outputs and a plurality of logic elements coupled together to form at least one path from a logic design input to one or more logic design outputs via the plurality of logic elements, wherein a logic element includes at least one logic element input and at least one logic element output for coupling to other logic elements, the logic design inputs and the logic design outputs, wherein each logic element, logic element input, logic element output, logic design input and logic design output comprises a node, wherein one or more nodes exist on the paths, the method executing on a computer system operated by a human user, the computer system including a processor coupled to a user input device and an output device, the method comprising the steps of:

(a) inputting a timing specification by a user using the user input device, wherein the timing specification comprises a timing parameter assigned to a first user-selected node in a path;

(b) using the processor to identify a path that originates at a logic design input, passes through the first node, and terminates at a logic design output;

(c) using the processor to determine a timing property of an electrical signal transmitted through the identified path, wherein the timing property corresponds with the timing parameter;

(d) using the processor to compare the timing property of the identified path with the timing parameter; and

(e) using the output device to indicate the relationship of the identified path'"'"'s timing property to the timing parameter.

2. The method of claim 1, wherein the identified path includes a first logic element, wherein the logic element output of the first logic element is coupled to the logic element inputs of at least two other logic elements.

3. The method of claim 1, wherein the timing parameter is a maximum propagation delay, wherein the timing property is the determined propagation delay of an electrical signal transmitted through the identified path.

4. The method of claim 1, wherein the logic design includes a clock input applied with a clock signal, wherein the timing parameter is a maximum delay from an active edge of the clock signal to registration of an output signal, wherein the step of using the processor to determine a timing property includes the substep of

using the processor to determine the delay from an active edge of the clock signal to registration of the output signal transmitted through the identified path.

5. The method of claim 1, wherein the logic design includes a clock input for receiving a clock signal, wherein the timing parameter is a minimum amount of time that a signal must be stable on an input before an active clock edge is received on the clock input, wherein the step of using the processor to determine a timing property includes the substep of

using the processor to determine, for the identified path, the amount of time that a signal must be stable at the input before an active clock edge is received.

6. The method of claim 1, wherein the logic design includes a clock input for receiving a clock signal, wherein the identified path includes a logic element with a predetermined setup/hold time, wherein the timing parameter is a maximum period for the clock signal, wherein the step of using the processor to determine a timing property includes the substep of

using the processor to determine, whether the maximum period for the clock exceeds the predetermined setup/hold time.

7. The method of claim 1, further comprising the steps of:

accepting additional signals from the user input device to define an additional timing parameter at a second node, wherein the second node is on the identified path;

using the processor to determine which of the first and second nodes is closest to the output of the identified path; and

using the timing parameter corresponding to the node closest to the output of the identified path in steps (d) and (e).

8. The method of claim 1, further comprising the steps of:

accepting additional signals from the user input device to define a timing cut-off;

assigning the timing cut-off to a second node; and

discarding paths that pass through the second node from the processing of steps (c), (d), and (e).

9. An apparatus for processing timing specifications in a logic design, the apparatus comprising:

a computer system coupled to a user input device, an output device and a processor;

a logic design description included within the computer system, wherein the logic design description includes logic design inputs, logic design outputs and a plurality of logic elements wherein a logic element includes at least one logic element input and at least one logic element output for coupling to other logic elements, the logic design inputs and the logic design outputs, wherein each logic element, logic element input, logic element output, logic design input and logic design output comprises a node, wherein one or more nodes exist on the paths;

defining means for accepting signals from the user input device by a user to define a timing specification, comprising a timing parameter associated with a first node in a path;

identification means coupled to the processor for identifying a path that originates at a logic design input, passes through the first node, and terminates at a logic design output;

determining means coupled to the processor for determining a timing property of an electrical signal transmitted through the identified path, wherein the timing property is associated with the timing specification;

comparing means coupled to the processor for comparing the timing property of the identified path with the timing specification; and

indicating means coupled to the processor and the output device for outputing the relationship between the identified path'"'"'s timing property and the timing specification.