Large common mode input range CMOS amplifier

• US 5,574,401 A
• Filed: 06/02/1995
• Issued: 11/12/1996
• Est. Priority Date: 06/02/1995
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Spitalny, Paul A.
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US08/460,084
• Time in Patent Office: 529 Days
• Field of Search: 330/253, 330/254, 330/257, 330/258, 330/261
• US Class Current: 330/253
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2203/45454 the CSC comprising biasing means controlled by the input signal
• CPC Class Codes: H03F 2203/45658 the LC comprising two diodes of current mirrors
• CPC Class Codes: H03F 2203/45674 the LC comprising one current mirror
• CPC Class Codes: H03F 2203/45708 the LC comprising one SEPP circuit as output stage
• CPC Class Codes: H03F 3/3023 with asymmetrical driving of the end stage
• CPC Class Codes: H03F 3/3027 using a common source driving stage, i.e. inverting stage
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel

Abstract

A CMOS amplifier input stage including an NMOS differential pair connected in parallel with a PMOS differential pair. Each pair is connected to a tail-current transistor of the same type, and the combined circuits are coupled between positive and negative supply rails. The gates of the tail-current transistors receive the amplifier input signal to provide adaptive biasing of the differential pairs, resulting in a total combined transconductance for both differential pairs which is at least approximately constant with changes in input signal level, thereby enlarging the available common-mode input signal range of the amplifier.

Claims

1. An amplifier comprising:

a differential pair of NMOS transistors;

an NMOS transistor connected to said NMOS differential pair to conduct the tail current thereof;

a differential pair of PMOS transistors;

a PMOS transistor connected to said PMOS differential pair to conduct the tail current thereof;

means connecting said NMOS differential pair together with said tail current NMOS transistor between two supply rails;

means connecting said PMOS differential pair together with said tail current PMOS transistor between said supply rails;

first and second input terminals to provide an input signal to said NMOS and PMOS differential pairs;

means responsive to the input signal for controlling said tail-current NMOS and PMOS transistors to effect adaptive biasing of said transistors; and

means to combine the outputs of said differential pairs to produce a composite output signal.

2. An amplifier as claimed in claim 1, wherein said input signal is directed to-the gates of said tail-current transistors.

3. An amplifier as claimed in claim 1, wherein said tail-current transistors operate as variable resistors in series with the corresponding differential pair.

4. An amplifier as claimed in claim 1, wherein each of the gates of said tail-current transistors is connected to an input terminal.

5. An amplifier as claimed in claim 4, wherein said gates are connected to the same input terminal.

6. In a CMOS amplifier having NMOS and PMOS differential pairs connected in parallel;

the method of extending the amplifier operating range comprising;

controlling the tail currents of both of said differential pairs in accordance with the square of variations in the input signal to said differential pairs; and

combining the outputs of said differential pairs.

7. The method of claim 6, wherein said tail currents are controlled by passing them through MOS transistors the gates of which are supplied with signals derived from said input signal.

8. In a CMOS amplifier having NMOS and PMOS differential pairs connected in parallel between supply rails, the method of extending the amplifier input signal range comprising:

control means for controlling the tail currents of both of said differential pairs in a way to maintain an effectively constant transconductance of both differential pairs;

said control means comprising series variable impedance means through which said tail current flows;

said variable impedance means including a control electrode for varying the magnitude of impedance in accordance with the magnitude of voltage of said control electrode;

means for applying to said control electrode a control signal directly corresponding to the amplifier input signal; and

combining the outputs of both differential pairs to form a composite output signal.

10. An amplifier as in claim 8 wherein said variable impedance means comprises a transistor having a control electrode receiving said control signal.

11. An amplifier as in claim 10 wherein said transistor is an FET device.

9. In a CMOS amplifier having NMOS and PMOS differential pairs connected in parallel between supply rails, the method of extending the amplifier input signal range comprising:

controlling the tail currents of said differential pairs in a way to maintain an effectively constant transconductance of both differential pairs by controling the tail currents so that they are made proportional to the square of the input signal level; and

combining the outputs of both differential pairs to form a composite output signal.