True/complementer for a half-band filter

• US 5,574,671 A
• Filed: 06/05/1995
• Issued: 11/12/1996
• Est. Priority Date: 08/14/1992
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Manion, Cindy C., Damarow, David H., Frogge, Perry W., Young, William R.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US08/462,684
• Time in Patent Office: 526 Days
• Field of Search: 364/715.03, 341/93
• US Class Current: 708/204
• CPC Class Codes: G06F 7/48 using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H03H 19/00 Networks using time-varying elements, e.g. N-path filters

Abstract

A digital half-band filter with mutliplications using Wallace trees which have lower bits truncated for reduction in size and with a true/complementer providing saturation compensation together with accumulator overflow compensation by monitoring bits more significant than the output bits.

Claims

1. A two'"'"'s complement format true/complementer, comprising:

plural cells Cj, j=0, 1, . . . , N, with each of said cells Cj having a data bit input, a saturation bit input, a carry bit input, a true/complement bit input, an overflow bit input, an overflow data bit input, and a bit memory coupled to said inputs;

saturation circuitry with inputs coupled to said data bit inputs of said cells Cj and an output coupled to said saturation bit inputs of cells Cj, said saturation circuitry detecting the condition of a bit at the data bit input of CN being a 1 and the bit at the data bit input of Cj being 0 for all j not equal to N, said saturation circuitry outputting a bit indicative of said condition; and

logic circuitry coupled to said inputs of said cells and to said saturation circuitry for (i) when a bit at said true/complement bit input indicates true, said bit memory of cell Cj stores a bit equal to the bit at said data bit input, and (ii) when a bit at said true/complement bit input indicates complement, said bit memory of cell Cj stores a bit equal to the complement of the bit at said data bit input plus the bit at said carry bit input, but (iii) when the bit at said overflow input indicates an overflow in the bits at said data bit inputs of said cells Cj said memory of cell Cj stores the bit at the overflow data bit input, and (iv) when the bit output by said saturation circuitry indicates said condition and when the bit at said true/complement bit input indicates complement said memory of cell CN stores 0 and said memory of cells Cj store 1 for j not equal to N.

2. The true/complementer of claim 1, wherein said bit memory of cell Cj comprises means for storing the bit in accordance with the bits and the bit inputs when said cell Cj is enabled and clocked.

3. The true/complementer of claim 1, further comprising lookahead carry circuitry coupled to said data bit inputs and said carry bit inputs for carrying a one when forming two'"'"'s complements.

4. The true/complementer of claim 1, wherein said logic circuitry further comprises an OR gate driven by said saturation bit input and said carry bit input;

a NAND gate driven by said true/complement bit input and the output of said OR gate; and

a multiplexer which multiplexes said overflow data bit input and said data bit input, and wherein the multiplexed output from said multiplexer and the output of said NAND gate drive an exclusive NOR gate which drives said memory.

5. The true/complementer of claim 1 wherein said logic circuitry comprises an AND gate for providing said true/complement bit input in response to receipt of the bit at said overflow bit input and a bit at a complementing bit input.

6. The true/complementer of claim 1 wherein N is seventeen.

7. A two'"'"'s complement format true/complementer, comprising:

plural cells Cj, j=0, 1, . . . , N, with each of said cells Cj having a data bit input, a saturation bit input, a carry bit input, a true/complement bit input, and a bit memory coupled to said inputs;

saturation circuitry with inputs coupled to said data bit inputs of said cells Cj and an output coupled to said saturation bit inputs of cells Cj, said saturation circuitry detecting the condition of a bit at the data bit input of CN being a 1 and the bit at the data bit input of Cj being 0 for all j not equal to N, said saturation circuitry outputting a bit indicative of said condition; and

logic circuitry coupled to said inputs of said cells and to said saturation circuitry for (i) when a bit at said true/complement bit input indicates true, said bit memory of cell Cj stores a bit equal to the bit at said data bit input, and (ii) when a bit at said true/complement bit input indicates complement, said bit memory of cell Cj stores a bit equal to the complement of the bit at said data bit input plus the bit at said carry bit input, and (iii) when the bit output by said saturation circuitry indicates said condition and when the bit at said true/complement bit input indicates complement said memory of cell CN stores 0 and said memory of cells Cj store 1 for j not equal to N.

8. The true/complementer of claim 7 further comprising lookahead carry circuitry coupled to said data bit inputs and said carry bit inputs for carrying a one when forming two'"'"'s complements.

9. The true/complementer of claim 7 wherein N is sixteen.

10. The true/complementer of claim 7 wherein said logic circuitry further comprises,

an OR gate driven by said saturation bit input and said carry bit input, and

a NAND gate driven by said true/complement bit input and the output of said OR gate.

11. The true/complementer of claim 10 further comprising an overflow data bit input to said cells Cj, and wherein said logic circuitry further comprises a multiplexer which multiplexes said overflow data bit input and said data bit input, and wherein the multiplexed output from said multiplexer and the output of said NAND gate drive an exclusive NOR gate which drives said memory.