Memory device with distributed voltage regulation system
First Claim
1. A memory device comprising:
- a memory cell array;
a plurality of control circuits operatively coupled to the array; and
a voltage regulation system including;
an array power bus operatively coupled to the array for distributing an array supply voltage to the array;
a control circuit power bus operatively coupled to the plurality of control circuits for distributing a control circuit supply voltage to the plurality of control circuits;
a first regulator circuit operatively coupled to the array power bus at a first location along the array power bus for providing and regulating the array supply voltage;
a second regulator circuit operatively coupled to the control circuit power bus at a first location along the control circuit power bus for providing and regulating the control circuit supply voltage; and
a third regulator circuit operatively coupled to either the array power bus or the control circuit power bus at a second location spaced apart from the first location for providing and regulating the array or control circuit supply voltage, respectively, thereby allowing the third regulator circuit to respond to a localized variation in the array or control circuit supply voltage, respectively, at the second location.
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Accused Products
Abstract
A memory device includes a memory cell array, control circuits, and a voltage regulation system. The voltage regulation system includes an array power bus distributing an array supply voltage to the array, and a control circuit power bus distributing a control circuit supply voltage to the control circuits. Regulator circuits are coupled to the array power bus at spaced-apart locations along the bus which allow each regulator circuit to respond independently to a localized variation in the array supply voltage. Other regulator circuits are similarly coupled to the control circuit power bus. The regulator circuits which are unneeded for a particular operating mode of the memory device can be turned off during active memory cycles, and all the regulator circuits can be turned off during stand-by memory cycles. A resistor couples the array and control circuit power busses, and a low-power regulator circuit is coupled to the control circuit power bus to maintain both the array and control circuit supply voltages during stand-by memory cycles while the regulator circuits are off. The voltage regulation system thus advantageously reduces the power consumption of the memory device by using the low-power regulator circuit alone during stand-by memory cycles, reduces noise from the array on the control circuit supply voltage by splitting the array and control circuit power busses, and provides more responsive regulation of the array and control circuit supply voltages by distributing the regulator circuits.
67 Citations
17 Claims
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1. A memory device comprising:
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a memory cell array; a plurality of control circuits operatively coupled to the array; and a voltage regulation system including; an array power bus operatively coupled to the array for distributing an array supply voltage to the array; a control circuit power bus operatively coupled to the plurality of control circuits for distributing a control circuit supply voltage to the plurality of control circuits; a first regulator circuit operatively coupled to the array power bus at a first location along the array power bus for providing and regulating the array supply voltage; a second regulator circuit operatively coupled to the control circuit power bus at a first location along the control circuit power bus for providing and regulating the control circuit supply voltage; and a third regulator circuit operatively coupled to either the array power bus or the control circuit power bus at a second location spaced apart from the first location for providing and regulating the array or control circuit supply voltage, respectively, thereby allowing the third regulator circuit to respond to a localized variation in the array or control circuit supply voltage, respectively, at the second location. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A computer system comprising:
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an input device; an output device; a processor operatively coupled to the input and output devices; and a memory device operatively coupled to the processor, the memory device comprising; a memory cell array; a plurality of control circuits operatively coupled to the array; and a voltage regulation system including; an array power bus operatively coupled to the array for distributing an array supply voltage to the array; a control circuit power bus operatively coupled to the plurality of control circuits for distributing a control circuit supply voltage to the plurality of control circuits; a first regulator circuit operatively coupled to the array power bus at a first location along the array power bus for providing and regulating the array supply voltage; a second regulator circuit operatively coupled to the control circuit power bus at a first location along the control circuit power bus for providing and regulating the control circuit supply voltage; and a third regulator circuit operatively coupled to either the array power bus or the control circuit power bus at a second location spaced apart from the first location for providing and regulating the array or control circuit supply voltage, respectively, thereby allowing the third regulator circuit to respond to a localized variation in the array or control circuit supply voltage, respectively, at the second location. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A voltage regulation system for a memory device having a memory cell array and a plurality of control circuits, the voltage regulation system comprising:
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an array power bus for distributing an array supply voltage to the array; a first plurality of regulator circuits each operatively coupled to the array power bus for providing and regulating the array supply voltage, the regulator circuits being coupled to the array power bus at spaced-apart locations along the bus to allow the regulator circuits to respond independently to a localized variation in the array supply voltage at their respective locations, each regulator circuit including a stand-by circuit to turn off the regulator circuit during stand-by cycles of the memory device; a control circuit power bus for distributing a control circuit supply voltage to the plurality of control circuits; a second plurality of regulator circuits each operatively coupled to the control circuit power bus for providing and regulating the control circuit supply voltage, the regulator circuits being coupled to the control circuit power bus at spaced-apart locations along the bus to allow the regulator circuits to respond independently to a localized variation in the control circuit supply voltage at their respective locations, each regulator circuit including a stand-by circuit to turn off the regulator circuit during stand-by cycles of the memory device; a low-power regulator circuit operatively coupled to the control circuit power bus for providing and regulating the control circuit supply voltage during stand-by cycles of the memory device while the first and second pluralities of regulator circuits are off; and a resistive device coupling the array and control circuit power busses so that the low-power regulator circuit can regulate both the array supply voltage and the control circuit supply voltage during stand-by cycles of the memory device.
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Specification