Scan-based built-in self test (BIST) with automatic reseeding of pattern generator

• US 5,574,733 A
• Filed: 07/25/1995
• Issued: 11/12/1996
• Est. Priority Date: 07/25/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kim, Kee S.
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/506,661
• Time in Patent Office: 476 Days
• Field of Search: 371/27, 371/22.3, 371/22.4, 371/22.5, 371/22.6, 377/72, 377/64
• US Class Current: 714/728
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A scan chain and method of generating non-successive pseudo-random test patterns for performing a built-in self test (BIST) on a circuit block in an integrated circuit. The scan chain includes a linear feedback shift register (LFSR) cascaded with a shift register. An output of a last storage element of the shift register is fed back in to an input of a first storage element of the LFSR such that the shift register and LFSR form a circular path. A first test pattern is generated in the scan chain when a data string stored in the shift register is shifted through the LFSR. The test pattern is then asserted on inputs of the circuit block. The circuit response is stored in the scan chain, and the scan chain is shifted once more in order to compress the result and generate a second test pattern simultaneously.

Claims

1. A method of generating non-successive pseudo-random test patterns for testing a circuit block in an integrated circuit, the method comprising the steps of:

a) generating a first test pattern in a scan chain that includes a linear feedback shift register (LFSR) being cascaded with a shift register, the scan chain further includes a feedback path which is formed by connecting the output of the shift register to the input of the LFSR, said generating step is performed by shifting first contents of the shift register of the scan through the LFSR by means of the feedback path of the scan chain;

b) asserting the generated first test pattern at inputs of the circuit block;

c) storing outputs from the circuit block in the scan chain; and

d) generating a second, non-successive, test pattern in the scan chain by shifting second contents of the shift register through the LFSR by means of said feedback path, wherein the LFSR generates the second test pattern according to a characteristic polynomial.

2. A method of performing a built-in self test (BIST) on a circuit block of an integrated circuit, the method comprising the steps of:

a) setting contents of a scan chain to an initial value, wherein the scan chain includes a linear feedback shift register (LFSR) cascaded with a shift register, and wherein an output of a last storage element in the scan chain is fed back to an input of a first storage element of the LFSR such that contents of the shift register are shifted through the LFSR upon application of a test clock;

b) generating a test pattern in the scan chain by applying the test clock N times, such that a data string of length N stored in the shift register is shifted through the LFSR, wherein the LFSR generates the test pattern according to a characteristic polynomial; and

c) applying the test pattern of the scan chain to inputs of the circuit block.

3. The method of claim 2, wherein step (a) further includes the step of first placing the integrated circuit in a test mode.

4. The method of claim 2, wherein step (c) further includes the step of first placing the integrated circuit in a system mode.

5. The method of claim 2, further comprising the steps of:

d) subsequent to step (c), loading outputs from the circuit block in to the scan chain; and

e) creating a signature value in the LFSR by applying the test clock N times such that the contents of the shift register are shifted through the LFSR and compressed according to a characteristic polynomial of the LFSR.

6. The method of claim 5, wherein step (e) further comprises the step of first placing the integrated circuit in a test mode.

7. The method of claim 5, wherein step (e) further comprises the step of simultaneously creating a second, non-successive, test pattern in the scan chain.

8. The method of claim 2, further comprising the steps of:

d) subsequent to step (c), loading outputs from the circuit block in to the scan chain; and

e) repeating steps (b) and (c) until a predetermined time at which the BIST sequence is to conclude.

9. The method of claim 2, wherein setting the contents of the scan chain to an initial value in step (a) further comprises serially scanning an initial test seed in to the LFSR.

10. The method of claim 2, wherein setting the contents of the scan chain to an initial value in step (a) further comprises resetting the contents of the scan chain to a zero value.

11. A scan chain for use in a built-in self test (BIST) sequence performed on a circuit block in an integrated circuit, the scan chain comprising:

a) a linear feedback shift register (LFSR); and

b) a shift register cascaded with the LFSR and coupled in a circular path wherein an output of a last storage element of the shift register is fed back to an input of a first storage element of the LFSR such that when a test clock is asserted, contents of the shift register are shifted through the LFSR such that a pseudo-random test pattern is generated in the scan chain.

12. The scan chain of claim 11 wherein the LFSR is a primitive polynomial LFSR.

13. The scan chain of claim 11 wherein the circular path further comprises an XOR gate coupled between the output of the last storage element of the shift register and the input of the first storage element of the LFSR.

14. The scan chain of claim 11 wherein the shift register further comprises a plurality of cascaded scan flip-flops.

15. A microprocessor capable of performing a built-in self test (BIST) comprising:

a) a circuit block;

b) a scan chain, including

a linear feedback shift register (LFSR), and

a shift register cascaded with the LFSR and coupled in a circular path wherein an output of a last storage element of the shift register is fed back to an input of a first storage element of the LFSR such that when a test clock is asserted, contents of the shift register are shifted through the LFSR such that a pseudo-random test pattern is generated in the scan chain.

16. The microprocessor of claim 15 wherein the LFSR is a primitive polynomial LFSR.

17. The microprocessor of claim 15 wherein the circular path further comprises an XOR gate coupled between the output of the last storage element of the shift register and the input of the first storage element of the LFSR.

18. The microprocessor of claim 15 wherein the shift register further comprises a plurality of cascaded scan flip-flops.

19. A scan chain for generating non-successive pseudo-random test patterns for testing a circuit block in an integrated circuit, the scan chain comprising:

a) pattern generation means for generating a plurality of pseudo-random test patterns, each test pattern being successively ordered, wherein each test pattern is generated from a test seed in accordance with a characteristic polynomial;

b) coupling means for applying the generated plurality of pseudo-random test patterns to inputs of the circuit block in the integrated circuit and receiving corresponding outputs from the circuit block; and

c) reseeding means for automatically providing the pattern generation means with the outputs from the circuit block, wherein the outputs from the circuit block are used as a test seed for a subsequent pseudo-random test pattern generated by the pattern generation means such that the subsequent pseudo-random test pattern is non-successive.