Method for generating digital communication system clock signals & circuitry for performing that method

• US 5,574,756 A
• Filed: 10/31/1994
• Issued: 11/12/1996
• Est. Priority Date: 05/25/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Deog-Kyoon
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): TRAN, CONGVAN
• Application Number:
  US08/332,561
• Time in Patent Office: 743 Days
• Field of Search: 375/376, 375/371, 375/373, 375/375, 375/344, 375/327, 327/147, 327/156, 327/159, 331/25, 331/34, 455/255, 455/258, 455/259, 455/260, 329/307, 329/308, 329/309, 329/310, 329/325
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A clock generating circuit generates 2n clocks (where n is a positive integer number) each having 1/2n frequency of a maximum baud rate of data bit-stream input and a phase difference of π/n between successive phases thereof, and simultaneously shifts the phases on the clocks ahead or behind until the phases between the clocks and corresponding data bits of the data bit-stream input are locked in quadrature, by comparing the phase of the clock with those of data bit-stream input and adjusting the phases of the clocks.

Claims

1. A method for phase-locking an output clock to an input signal with input signal transitions between "0" and "1" logic levels, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said method comprising the steps of:

generating an output clock exhibiting transitions between "0" and "1" conditions at an output frequency that is substantially the same as said input frequency;

assigning consecutive transitions of said output clock cyclically to first through m^th sets of transitions of said output clock, m being an integer more than one;

controlling the delay of each of said first through m^th sets of transitions of said output clock in response to a control signal, for generating first through m^th sets of delayed transitions of said output clock;

detecting when the respective delayed transitions of each of said first through m^th sets of delayed transitions of said output clock occur at times other than at midpoints of said symbol periods, thus to generate a respective one of m error signal components;

combining all m of said error signal components to generate an error signal; and

lowpass filtering said error signal for generating said control signal.

2. A method as set forth in claim 1 for phase-locking an output clock to an input signal with input signal transitions between "0" and "1" logic levels, wherein said input signal is an input clock with transitions between "0" and "1" logic levels at said input frequency.

3. A method for phase-locking an output clock to an input clock with transitions between "0" and "1" logic levels at ones of intervals occurring at an input frequency, said method comprising the steps of:

generating an output clock exhibiting transitions between "0" and "1" conditions at an output frequency that is substantially the same as said input frequency;

assigning consecutive transitions of said output clock cyclically to first through m^th sets of transitions of said output clock, m being an integer more than one;

controlling the delay of each of said first through m^th sets of transitions of said output clock in response to a control signal, for generating first through m^th sets of delayed transitions of said output clock;

performing a phase comparison of said delayed transitions of said output clock in each of said first through m^th sets thereof with corresponding transitions in said input clock, thus to generate a respective one of m error signal components;

combining all m of said error signal components to generate an error signal; and

lowpass filtering said error signal for generating said control signal.

4. The method for phase-locking an output clock to an input clock set forth in claim 3 included as steps in a method for phase-locking said output clock to a data stream, which method for phase-locking said output clock to a data stream additionally comprises the preliminary steps of:

detecting symbol transitions in said data stream; and

generating said input clock with its transitions between "0" and "1" logic levels substantially coinciding in time with said symbol transitions.

5. A method for phase-locking an output clock to an input clock with transitions between "0" and "1" logic levels at ones of intervals occurring at an input frequency, said method comprising the steps of:

generating a multiple-phase output clock exhibiting transitions between "0" and "1" at an output frequency that is the same as said input frequency, said multiple-phase output clock comprising a plurality of component clocks each of a frequency that is a submultiple of said input frequency;

controlling the delay of said multiple-phase output clock in response to a control signal, thereby to delay each of said plurality of component clocks in like amount for generating a respective delayed response to each of said component clocks;

comparing the phase of said input clock with the phase of each of said respective delayed responses to said component clocks, thus to generate a respective component of an error signal;

combining all of said components of said error signal to generate said error signal; and

lowpass filtering said error signal for generating said control signal.

6. The method for phase-locking an output clock to an input clock set forth in claim 5 included as steps in a method for phase-locking said output clock to a data stream, which method for phase-locking said output clock to a data stream additionally comprises the preliminary steps of:

detecting symbol transitions in said data stream; and

generating said input clock with its transitions between "0" and "1" logic levels substantially coinciding in time with said symbol transitions.

7. A method for phase-locking an output clock to an input clock with transitions between "0" and "1" logic levels at ones of intervals occurring at an input frequency, said method comprising the steps of:

generating a multiple-phase output clock exhibiting transitions between "0" and "1" at an output frequency that is the same as said input frequency, said multiple-phase output clock comprising a plurality of component clocks each of a frequency that is a submultiple of said input frequency;

controlling the delay of said multiple-phase output clock in response to a control signal, thereby to delay each of said plurality of component clocks in like amount for generating a respective delayed response to each of said component clocks;

comparing the phase of said input clock with the phases of said respective delayed responses to each of said component clocks;

constructively combining the results of comparing the phase of said input clock with the phases of said respective delayed responses to each of said component clocks, thus to generate an error signal; and

lowpass filtering said error signal for generating said control signal.

8. The method for phase-locking an output clock to an input clock set forth in claim 7 included as steps in a method for phase-locking said output clock to a data stream, which method for phase-locking said output clock to a data stream additionally comprises the preliminary steps of:

detecting symbol transitions in said data stream; and

generating said input clock with its transitions between "0" and "1" logic levels substantially coinciding in time with said symbol transitions.

9. A method for generating a clock in a digital communication system which said clock is phase-synchronized with symbols in a data input signal, which said symbols occur at a symbol rate, said method for generating a clock comprising steps of:

generating 2n clocks each having a predetermined same frequency which is a submultiple of said symbol rate and having phase delay of π

/n between successive ones of said 2n clocks, n being a positive integer;

comparing the phasing of each of said 2n clocks respective to said symbols to detect any misphasing therefrom as an error signal component;

loop-filtering for supplying a phase control signal in response to said error signal components; and

phase controlling for simultaneously shifting the phases of the clocks ahead or behind in response to said phase control signal until the edges of said 2n clocks occur at the midpoints of said symbol periods.

10. A method for generating a clock in a digital communication system which said clock is phase-synchronized with symbols in a data input signal, said method for generating a clock comprising steps of:

generating 2n clocks each having a frequency corresponding to 1/2/n times a maximum baud rate for said data stream input, with a phase delay of π

/n between successive ones of said 2n clocks;

comparing the phasing of said 2n clocks respective to said symbols to detect any misphasing therefrom as an error signal;

loop-filtering for supplying a phase control signal in response to said error signal; and

phase controlling for simultaneously shifting the phases of the clocks ahead or behind in response to said phase control signal until the edges of said 2n clocks occur at the midpoints of said symbol periods.

11. A clock generating circuit for generating an output clock phase-locked with an input signal with input signal transitions between "0" and "1" logic levels, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said clock generating circuit comprising:

a clock generator for generating m component clocks of an m-phase output clock, m being an integer greater than one, each of said m component clocks having a frequency (1/m) times said input frequency and having a different respective phase with respect to each other of said component clocks, each of which different respective phases is expressible as a positive multiple less than m of 2π

/m radians;

a detector for detecting any misphasing of said m component clocks from midpoints of said symbol periods to generate an error signal;

a loop filter for supplying a phase control signal in response to said error signal supplied from said phase detector; and

a phase controller responsive to said phase control signal for simultaneously shifting the phases of said m component clocks ahead or behind so as to reduce any misphasing of the edges of said m component clocks respective to said input signal transitions.

12. A clock generating circuit as set forth in claim 11, wherein said input signal is an input clock with transitions between "0" and "1" logic levels at said input frequency, and wherein said detector for detecting any misphasing of said m component clocks from midpoints of said symbol periods comprises:

a phase detector for comparing the phasing of said m component clocks respective to said transitions between "0" and "1" logic levels of said input clock to generate said error signal.

13. A clock generating circuit as set forth in claim 12 included in a digital communication system for generating a clock phase-locked in quadrature phasing with symbol transitions in an input data stream, said digital communication system also including:

a symbol transition detector for detecting symbol transitions occurring between symbol periods in said data stream and generating an input clock with said transitions between "0" and "1" logic levels at said input frequency, which said input clock transitions coincide in time with said symbol transitions.

14. A clock generating circuit as set forth in claim 13, wherein said m clocks each are of a frequency that is 1/2m times a maximum baud rate of said input data.

15. A clock generating circuit as claimed in claim 12, wherein said loop filter comprises:

a capacitor for supplying between first and second plates thereof said phase control signal; and

a differential transconductance amplifier responding to said error signal supplied from said phase detector for changing the charge stored within said capacitor, charging said capacitor when said error signal is of a first sense of polarity and discharging said capacitor when said error signal is of a second sense of polarity opposite to said first sense of polarity.

16. A clock generating circuit for generating an output clock phase-locked with an input clock with transitions between "0" and "1" logic levels at ones of intervals occurring at an input frequency, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said clock generating circuit comprising:

a clock generator for generating m component clocks of an m-phase output clock, m being an even integer that is twice another integer n greater than one, each of said m component clocks exhibiting respective transitions between "0" and "1" logic levels thereof, having a frequency (1/m) times said input frequency, and having a different respective phase with respect to each other of said component clocks, each of which different respective phases is expressible as a positive multiple less than m of 2π

/m radians;

a phase detector comparing the phasing of said m component clocks respective to said transitions between "0" and "1" logic levels of said input clock, for detecting any misphasing of said m component clocks from midpoints of said symbol periods to generate an error signal;

a loop filter for supplying a phase control signal in response to said error signal supplied from said phase detector; and

a phase controller responsive to said phase control signal for simultaneously shifting the phases of said m component clocks ahead or behind so as to reduce any misphasing of the edges of said m component clocks respective to said input clock;

wherein said phase detector comprises;

first and second nodes for supplying said error signal in push/pull;

third, fourth and fifth nodes;

biasing circuitry tending to pull respective potentials at said first node and at said second node in a first direction and tending to pull potential at said fifth node in a second direction opposite to said first direction;

means responsive to said input clock being at "0" logic level for selectively clamping said first node to said third node;

means responsive to said input clock being at "0" logic level for selectively clamping said second node to said fourth node;

means responsive to said input clock being at "1" logic level for selectively clamping said first node to said fourth node;

means responsive to said input clock being at "1" logic level for selectively clamping said second node to said third node; and

means for alternately clamping said third node and said fourth node to said fifth node, the alternation of said alternate clamping occurring in response to each change in said logic levels of said m component clocks of said m-phase output clock.

17. A clock generating circuit as set forth in claim 16, wherein said means for alternately clamping said third node and said fourth node to said fifth node comprises

first through n^th means for selectively providing a respective conductive path between said third node and said fifth node responsive to a respective pair of said m component clocks of said m-phase output clock;

and

(n+1)^th through 2n^th means for selectively providing a respective conductive path between said fourth node and said fifth node responsive to a respective pair of said m component clocks of said m-phase output clock.

18. A clock generating circuit as set forth in claim 16, wherein said biasing circuitry comprises:

a sixth node;

a first resistor connecting said first and sixth nodes;

a second resistor connecting said second and sixth nodes; and

means for causing substantially constant current to circulate through said fifth and sixth nodes.

19. A clock generating circuit as claimed in claim 16, wherein said loop filter comprises:

a capacitor for supplying between first and second plates thereof said phase control signal; and

a differential transconductance amplifier responding to said error signal supplied in push/pull from said first and second nodes for changing the charge stored within said capacitor, charging said capacitor when said error signal is of a first sense of polarity and discharging said capacitor when said error signal is of a second sense of polarity opposite to said first sense of polarity.

20. A clock generating circuit as set forth in claim 16 included in a digital communication system for generating a clock phase-locked in quadrature phasing with symbol transitions in an input data stream, said digital communication system also including:

a symbol transition detector for detecting symbol transitions occurring between symbol periods in said data stream and generating Uan input clock with said transitions between "0" and "1" logic levels at said input frequency, which said input clock transitions coincide in time with said symbol transitions.

21. A clock generating circuit as set forth in claim 20, wherein said m clocks each are of a frequency that is 1/2m times a maximum baud rate of said input data.

22. A clock generating circuit for generating an output clock phase-locked with an input signal with input signal transitions between "0" and "1" logic levels, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said clock generating circuit comprising:

a controlled oscillator for generating m component clocks of an m-phase output clock, m being an integer greater than one, each of said m component clocks having a frequency (1/m) times said input frequency and having a different respective phase with respect to each other of said component clocks, each of which different respective phases is expressible as a positive multiple less than m of 2π

/m radians, the phase of each of said m component clocks being adjustable responsive to a control signal received by said controlled oscillator;

a detector for detecting any misphasing of said m component clocks from midpoints of said symbol periods to generate an error signal;

a loop filter for supplying said control signal in response to said error signal supplied from said phase detector.

23. A clock generating circuit as set forth in claim 22, wherein said input signal is an input clock with transitions between "0" and "1" logic levels at said input frequency, and wherein said detector for detecting any misphasing of said m component clocks from midpoints of said symbol periods comprises a phase detector for comparing the phasing of said m component clocks respective to said input clock to generate said error signal.

24. A clock generating circuit as set forth in claim 23 included in a digital communication system for generating a clock phase-locked in quadrature phasing with symbol transitions in an input data stream, said digital communication system also including:

a symbol transition detector for detecting symbol transitions occurring between symbol periods in said data stream and generating said input clock with said transitions between "0" and "1" logic levels at said input frequency, which said input clock transitions coincide in time with said symbol transitions.

25. A clock generating circuit as set forth in claim 24, wherein said m clocks each are of a frequency that is 1/2m times a maximum baud rate of said input data.

26. A clock generating circuit for generating an output clock phase-locked with an input clock with transitions between "0" and "1" logic levels at ones of intervals occurring at an input frequency, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said clock generating circuit comprising:

a controlled oscillator for generating m component clocks of an m-phase output clock, m being an integer greater than one, each of said m component clocks exhibiting respective transitions between "0" and "1" logic levels thereof, having a frequency (1/m) times said input frequency, and having a different respective phase with respect to each other of said component clocks, each of which different respective phases is expressible as a positive multiple less than m of 2π

/m radians, the phase of each of said m component clocks being adjustable responsive to a control signal received by said controlled oscillator;

a phase detector comparing the phasing of said m component clocks respective to said transitions between "0" and "1" logic levels of said input clock, for detecting any misphasing of said m component clocks from midpoints of said symbol periods to generate an error signal; and

a loop filter for supplying a phase control signal in response to said error signal supplied from said phase detector;

wherein said phase detector comprises;

first and second nodes for supplying said error signal in push/pull;

third, fourth and fifth nodes;

biasing circuitry tending to pull respective potentials at said first node and at said second node in a first direction and tending to pull potential at said fifth node in a second direction opposite to said first direction;

means responsive to said input clock being at "0" logic level for selectively clamping said first node to said third node;

means responsive to said input clock being at "0" logic level for selectively clamping said second node to said fourth node;

means responsive to said input clock being at "1" logic level for selectively clamping said first node to said fourth node;

means responsive to said input clock being at "1" logic level for selectively clamping said second node to said third node; and

means for alternately clamping said third node and said fourth node to said fifth node, the alternation of said alternate clamping occurring in response to each change in said logic levels of said m component clocks of said m-phase output clock.

27. A clock generating circuit as set forth in claim 26, wherein said means for alternately clamping said third node and said fourth node to said fifth node comprises

first through n^th means for selectively providing a respective conductive path between said third node and said fifth node responsive to a respective pair of said m component clocks of said m-phase output clock;

and

(n+1)^th through 2n^th means for selectively providing a respective conductive path between said fourth node and said fifth node responsive to a respective pair of said m component clocks of said m-phase output clock.

28. A clock generating circuit as set forth in claim 26, wherein said biasing circuitry comprises:

a sixth node;

a first resistor connecting said first and sixth nodes;

a second resistor connecting said second and sixth nodes; and

means for causing substantially constant current to circulate through said fifth and sixth nodes.

29. A clock generating circuit as claimed in claim 26, wherein said loop filter comprises:

a capacitor for supplying between first and second plates thereof said control signal; and

a differential transconductance amplifier responding to said error signal supplied in push/pull from said first and second nodes for changing the charge stored within said capacitor, charging said capacitor when said error signal is of a first sense of polarity and discharging said capacitor when said error signal is of a second sense of polarity opposite to said first sense of polarity.

30. A clock generating circuit as set forth in claim 26 included in a digital communication system for generating a clock phase-locked in quadrature phasing with symbol transitions in an input data stream, said digital communication system also including:

a symbol transition detector for detecting symbol transitions occurring between symbol periods in said data stream and generating said input clock with said transitions between "0" and "1" logic levels at said input frequency, which said input clock transitions coincide in time with said symbol transitions.

31. A clock generating circuit as set forth in claim 30, wherein said m clocks each are of a frequency that is 1/2m times a maximum baud rate of said input data.