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Method for generating digital communication system clock signals & circuitry for performing that method

  • US 5,574,756 A
  • Filed: 10/31/1994
  • Issued: 11/12/1996
  • Est. Priority Date: 05/25/1994
  • Status: Expired due to Term
First Claim
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1. A method for phase-locking an output clock to an input signal with input signal transitions between "0" and "1" logic levels, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said method comprising the steps of:

  • generating an output clock exhibiting transitions between "0" and "1" conditions at an output frequency that is substantially the same as said input frequency;

    assigning consecutive transitions of said output clock cyclically to first through mth sets of transitions of said output clock, m being an integer more than one;

    controlling the delay of each of said first through mth sets of transitions of said output clock in response to a control signal, for generating first through mth sets of delayed transitions of said output clock;

    detecting when the respective delayed transitions of each of said first through mth sets of delayed transitions of said output clock occur at times other than at midpoints of said symbol periods, thus to generate a respective one of m error signal components;

    combining all m of said error signal components to generate an error signal; and

    lowpass filtering said error signal for generating said control signal.

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