Computer graphics parallel system with temporal priority

• US 5,574,847 A
• Filed: 09/29/1993
• Issued: 11/12/1996
• Est. Priority Date: 09/29/1993
• Status: Expired due to Term

• Current Assignee: Evans & Sutherland Computer Corp. (Elevate Entertainment, Inc.)
• Original Assignee: Evans & Sutherland Computer Corp. (Elevate Entertainment, Inc.)
• Inventors: Armstrong, William, Eckart, Glen A.
• Primary Examiner(s): TUNG, KEE M
• Application Number:
  US08/128,893
• Time in Patent Office: 1,140 Days
• Field of Search: 395/121, 395/122, 395/126, 395/133, 395/134, 395/138, 395/139, 395/162-164, 395/800, 395/250, 395/325, 395/280, 395/284, 395/309, 395/310
• US Class Current: 345/505
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

Front end processors in a graphics architecture execute parallel scan conversion and shading to process individually assigned primitive objects for providing update pixels. A crossbar along with groups of first-in-first-out registers (FIFOs) accommodates data flow to parallel pixel processors with associated memory capabilities (frame buffer banks) where visibility and blending operations are performed on predetermined sequences of update pixels to provide frame buffer pixels and ultimately display pixels. The pixel processors identify with sequences of pixels in the display in patterns designed to equalize processor loads for pixels located along scan lines of a raster, or distributed over an area. Update pixel data is tagged to identify FIFO groups (pixel processors) individual FIFO selection and output sequence. Temporal priority is accomplished so that primitive data is entered in the frame buffer banks (components) restored to the same order as generated at the central processor (CPU) level.

Claims

1. A system for processing differing data sets as provided in temporal sequence to be processed as distinct packets, said system comprising:

a plurality of parallel processors, said processors being allowed differing processing operations on said differing data sets;

an output unit outputting said differing data sets in said temporal sequence;

a plurality of FIFOs coupled to said processors, a distinct FIFO being connected to one of said processors to allow independent operation of said one processor from remaining of said processors for accommodating said differing processing operations, said plurality of FIFOs being commonly coupled to said output unit; and

control means for said differing data sets flowing through said processors and said FIFOs to preserve said temporal sequence.

2. A system for processing data sets as provided in temporal sequence to be processed as distinct packets, said system comprising:

an input unit presenting an input operation of substantially a first duration, said data sets being provided to said input unit in said temporal sequence;

a processor providing a processing operation of substantially a second duration;

a plurality of N parallel output units providing output operations of substantially a third duration, said third duration being relatively greater than said first and second durations;

a plurality of N FIFOs coupled to said processor and further coupled to said output units in a one-to-one correspondence as between a distinct FIFO and a distinct output unit to isolate said output units from each other for preserving said temporal sequence of said data sets in said output units; and

control means for data sets flowing through said processor and said FIFOs to preserve said temporal sequence.

3. A system for processing data sets as provided in temporal sequence to be processed as distinct packets, said system comprising:

a plurality of N processors a coupled for parallel operation;

a plurality of M output units coupled for parallel operation;

an N×

M array of FIFOs coupled to said processors and output units whereby a FIFO distinctly connects one of said processors to one of said output units allowing independent operation of said one output unit from said one processor and from remaining of said output units; and

control means for data sets flowing through said processors, FIFOs and output units.

4. A system according to claim 3 wherein said processors comprise primitive processors, and said output units comprise visibility-and-blend processors.

5. A system according to claim 4 comprising N parallel primitive processors, M parallel visibility-and-blend processors and N×

M FIFOs.

6. A system according to claim 5 wherein said control means preserves said data sets in temporal sequence.

7. A system for processing data sets as provided in temporal sequence to be processed as distinct packets, said system comprising:

a plurality of N processors coupled for parallel operation;

a plurality of M output units coupled for parallel operation;

an N×

M array of FIFOs coupled to said processors and output units whereby a distinct one of said FIFOs connects one of said processors to one of said output units allowing independent operation of said one processor from said remaining of said processors and from said one output unit; and

control means for data sets flowing through said processors and said FIFOs to preserve said temporal sequence.

8. A graphics system for processing primitive data, as provided in a temporal sequence from a host computer, to provide display data in the form of display pixels related to locations in a display, said graphics system comprising:

a primitive structure for processing said primitive data to provide representative update pixels and comprising a plurality of primitive processors for iteratively receiving and processing primitive data in parallel for individual primitives, whereby said temporal sequence is altered;

a plurality of visibility-and-blend pixel processors, said visibility-and-blend processors each comprising an associated frame buffer bank for storing predetermined pixels related to locations in a display, said visibility-and-blend processors each for iteratively processing said update pixels into said associated frame buffer bank;

a switch structure for supplying said update pixels from said primitive structure to said visibility-and-blend pixel processors in accordance with locations in a display; and

a distribution structure for supplying said update pixels to said visibility-and-blend pixel processors in said temporal sequence.

9. A graphics system according to claim 8 wherein said primitive structure for processing said primitive data comprises means for scan converting said primitive data.

10. A graphics system according to claim 9 wherein said primitive structure for processing said primitive data further comprises means for shading said primitive data.

11. A graphics system according to claim 9 wherein said primitive processors receive primitive coherent data, said visibility-and-blend pixel processors receive screen space coherent data.

12. A graphics system according to claim 11 further comprising a display unit coupled to receive display sequence data.

13. A graphics system according to claim 8 wherein said visibility-and-blend pixel processors determine visibility between said update pixels and the content of said frame buffer bank to resolve contention.

14. A graphics system according to claim 8 wherein said visibility-and-blend pixel processors further comprise FIFOs for storing pixel data.

15. A graphics system according to claim 8 further comprising a display pixel multiplexer for receiving display pixels from said frame buffer banks to provide said display pixels in a display sequence.

16. A graphics system according to claim 15 wherein said display sequence is a raster pattern.

17. A graphics system according to claim 8 wherein each of said associated frame buffer banks stores display pixels for spaced apart locations in said display.

18. A graphics system according to claim 17 wherein said spaced apart locations are related to a raster scan pattern.

19. A method of parallel processing computer graphics object data specifying primitives to provide display data comprising the steps of:

receiving primitive data representative of primitives in a sequence of temporal priority;

scan converting said primitive data in a plurality of parallel operations to provide streams of update pixel data disordered with respect to said temporal priority;

storing said update pixel data for varying intervals to re-establish said temporal priority; and

processing said update pixel data iteratively in a plurality of parallel operations to store frame buffer pixels as display data.

20. A method according to claim 19, further comprising a step of shading said primitive data.

21. A method according to claim 19, wherein said step of processing comprises a step of determining visibility between said update pixel data and said frame buffer pixels to resolve contention.

22. A method according to claim 19, wherein said step of scan converting scan-converts primitive-coherent primitive data.

23. A method according to claim 19, wherein said step of processing processes screen-coherent update pixel data.

24. A method system according to claim 19 further comprising a step of storing said frame buffer pixels as display data according to display locations.

25. A method according to claim 19 further comprising a step of tagging said update pixel data for preserving temporal priority.

26. A method according to claim 19, further comprising a step of sorting said primitive data from primitive-coherent streams to screen-coherent streams.