Bus grant prediction technique for a split transaction bus in a multiprocessor computer system

• US 5,574,868 A
• Filed: 05/14/1993
• Issued: 11/12/1996
• Est. Priority Date: 05/14/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Marisetty, Suresh
• Primary Examiner(s): RUDOLPH, REBECCA
• Application Number:
  US08/062,065
• Time in Patent Office: 1,278 Days
• Field of Search: 395/325, 395/400, 395/425, 395/477, 395/478, 395/494, 395/496, 395/495, 395/287, 395/297, 395/293, 395/298
• US Class Current: 710/118
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/362 with centralised access control

Abstract

A early bus grant prediction technique combines the operating advantages of both a split transaction bus and a simple shared bus. When a read request is generated by a memory access requester, an early bus request is generated for the impending data transfer. The early bus request is provided to bus grant prediction and arbitration logic that determines whether or not the bus will be available at the time the requested data has been retrieved and is ready for transfer. If the bus is available, the retrieved data is routed immediately to the memory bus for a fly-by transfer. On the other hand, if the bus is not available, the data is routed to a FIFO buffer to be transferred when the bus is available.

Claims

1. A data processing system comprising:

(a) a data communication bus;

(b) a data memory;

(c) a data requester, coupled to the data communication bus, operable to issue a memory read request over the data communication bus for requested data stored in the data memory;

(d) a memory controller, coupled to the data communication bus and the data memory, operable to receive the memory read request and to issue read control signals to the data memory to retrieve the requested data, and to generate an early bus request signal as a function of the memory read request while access to the data memory is occurring to obtain the requested data;

(e) bus grant prediction logic, coupled to the data communication bus and the memory controller, operable to receive the early bus request signal and to generate a bus grant status signal in response thereto while access to the data memory is occurring to obtain the requested data, the bus grant status signal indicating a predicted future clock for availability of the data communication bus;

(f) data routing circuitry, coupled to the data memory, the memory controller and the data communication bus, operable to transfer the requested data retrieved from the data memory onto the data communication bus at the predicted future clock for availability indicated by the bus grant status signal.

2. The data processing system of claim 1, wherein the data routing circuitry transfers the requested data onto the data communication bus immediately upon receipt from the data memory.

3. The data processing system of claim 1, wherein the data routing circuitry comprises a data buffer for temporarily storing the requested data until the cycle for availability of the data communication bus.

4. The data processing system of claim 3, wherein the data routing circuitry further comprises a multiplexor, coupled to the data buffer, the data memory and the memory controller, operable to transfer the requested data onto the data communication bus directly from the data memory when the requested data is retrieved substantially concurrently with the cycle for availability of the data communication bus, and operable to transfer the requested data onto the data communication bus from the data buffer when the requested data is temporarily stored in the data buffer prior to the cycle for availability of the data communication bus.

5. In a data processing system having a data memory, a memory controller, and a shared data communication bus, a method of conducting a memory access transaction comprising the steps of:

(a) a data requester issuing a memory read request specifying requested data stored in the data memory;

(b) the memory controller decoding the read request to issue read control signals to the data memory for retrieving the requested data;

(c) the memory controller generating an early bus request signal as a function of the memory read request while access to the data memory is occurring to obtain the requested data;

(d) generating a bus grant status signal in a bus grant prediction unit in response to the early bus request signal while access to the data memory is occurring to obtain the requested data, the bus grant status signal indicating a predicted future cycle for availability of the data communication bus; and

(e) transferring the requested data retrieved from the data memory directly onto the data communication bus if the requested data is retrieved substantially concurrently with the predicted future cycle for availability of the data communication bus, and transferring the requested data into a data buffer if the requested data is retrieved prior to the predicted future cycle for availability of the data communication bus.

6. A memory access control system for a multiprocessor computer system having a data communication bus, a data memory, and a plurality of processors coupled to the data communication bus, any one of which issues a memory read request over the data communication bus for requested data stored in the data memory, the memory access control system comprising:

(a) a memory controller means, coupled to the data communication bus and the data memory, for receiving the memory read request, for issuing read control signals to the data memory to retrieve the requested data, and for generating an early bus request signal as a function of the memory read request while access to the data memory is occurring to obtain the requested data;

(b) bus grant prediction means, coupled to the data communication bus and the memory controller means, for receiving the early bus request signal and generating a bus grant status signal in response thereto while access to the data memory is occurring to obtain the requested data, the bus grant status signal indicating a predicted future cycle for availability of the data communication bus; and

(c) data routing means, coupled to the data memory, the memory controller means and the data communication bus, for transferring the requested data retrieved from the data memory onto the data communication bus at the predicted future cycle for availability indicated by the bus grant status signal.

7. The memory access control system of claim 6, wherein the data routing means transfers the requested data onto the data communication bus immediately upon receipt from the data memory.

8. The memory access control system of claim 6, wherein the data routing means comprises a data buffer means for temporarily storing the requested data until the cycle for availability of the data communication bus.

9. The memory access control system of claim 8, wherein the data routing means further comprises a multiplexor means, coupled to the data buffer, the data memory, the data communication bus and the memory controller, for transferring the requested data onto the data communication bus directly from the data memory when the requested data is retrieved substantially concurrently with the cycle for availability of the data communication bus, and for transferring the requested data onto the data communication bus from the data buffer when the requested data is temporarily stored in the data buffer prior to the cycle for availability of the data communication bus.

10. A data processing system comprising:

(a) a data communication bus;

(b) a data memory;

(c) a data requester, coupled to the data communication bus, operable to issue a memory read request over the data communication bus for requested data stored in the data memory;

(d) a memory controller, coupled to the data communication bus and the data memory, operable to receive the memory read request, to issue read control signals to the data memory to retrieve the requested data, and to generate an early bus request signal as a function of the memory read request while access to the data memory is occurring to obtain the requested data;

(e) bus grant prediction logic, coupled to the data communication bus and the memory controller, operable to receive the early bus request signal and to generate a bus grant status signal in response thereto while access to the data memory is occurring to obtain the requested data, the bus grant status signal indicating a predicted future time of availability of the data communication bus;

(f) a data buffer, coupled to the data memory and the memory controller, operable to temporarily store the requested data until the predicted future time of availability of the data communication bus; and

(g) a multiplexor, coupled to the data buffer, the data memory, the data communication bus and the memory controller, operable to transfer the requested data onto the data communication bus directly from the data memory when the requested data is retrieved substantially concurrently with the predicted future time of availability of the data communication bus, and operable to transfer the requested data onto the data communications bus from the data buffer when the requested data is temporarily stored in the data buffer prior to the predicted future time of availability of the data communication bus.

11. A memory access control system for a multiprocessor computer system having a data communication bus, a data memory, and a plurality of processors coupled to the data communication bus, any one of which issues a memory read request over the data communication bus for requested data stored in the data memory, the memory access control system comprising:

(a) a memory controller means, coupled to the data communication bus and the data memory, for receiving the memory read request, for issuing read control signals to the data memory to retrieve the requested data, and for generating an early bus request signal as a function of the memory read request while access to the data memory is occurring to obtain the requested data;

(b) bus grant prediction means, coupled to the data communication bus and the memory controller means, for receiving the early bus request signal and generating a bus grant status signal in response thereto while access to the data memory is occurring to obtain the requested data, the bus grant status signal indicating a predicted future time of availability of the data communication bus;

(c) a data buffer means, coupled to the data memory, the data communication bus and the memory controller means, for temporarily storing the requested data until the predicted future time of availability of the data communication bus; and

(d) a multiplexor means, coupled to the data buffer means, the data memory, the data communication bus and the memory controller means, for transferring the requested data onto the data communication bus directly from the data memory when the requested data is retrieved substantially concurrently with the predicted future time of availability of the data communication bus, and for transferring the requested data onto the data communication bus from the data buffer when the requested data is temporarily stored in the data buffer means prior to the predicted future time of availability of the data communication bus.