Method and apparatus for implementing a set-associative branch target buffer

• US 5,574,871 A
• Filed: 01/04/1994
• Issued: 11/12/1996
• Est. Priority Date: 01/04/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gupta, Ashwani K., Fetterman, Michael A., Hinton, Glenn J., D'Sa, Reynold V., Papworth, David B., Shenoy, Sunil, Hoyt, Bradley D., Natarajan, Subramanian
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US08/177,155
• Time in Patent Office: 1,043 Days
• Field of Search: 395/375
• US Class Current: 712/200
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer

Abstract

A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

Claims

1. A branch instruction prediction mechanism, said branch instruction prediction mechanism predicting a plurality of branch instructions within a stream of computer instructions, said branch instruction prediction mechanism comprising:

an instruction pointer for identifying an instruction address in a memory, said instruction pointer having a set of branch target buffer set address bits and a set of branch target buffer tag address bits;

a branch target buffer cache, said branch target buffer cache comprising a plurality of branch set entries, each of said branch set entries comprising a set of branch instruction entries, each branch instruction entry storing information about an associated branch instruction including a position with a memory block, all branch instruction entries within a particular branch set entry storing branch instructions having identical branch target buffer set address bits; and

a branch target buffer circuit, said branch target buffer circuit receiving said instruction pointer, said branch target buffer circuit indexing into said branch target buffer cache with said set of branch target buffer set address bits of said instruction pointer to select a branch set entry, said branch target buffer circuit selecting at least one branch instruction entry in said branch set entry using said branch target buffer tag address bits of said instruction pointer.

2. The branch instruction prediction mechanism as claimed in claim 1 wherein said instruction pointer points to a block of memory and said branch target buffer circuit searches for a first upcoming branch instruction in said block of memory pointed to by said instruction pointer.

3. The branch instruction prediction mechanism as claimed in claim 1 wherein each branch set entry further comprises a set of Least Recently Replaced Bits.

4. The branch instruction prediction mechanism as claimed in claim 1 wherein each said associated branch instruction stored into said branch target buffer cache is stored in said branch target buffer using an address of a last byte of each associated branch instruction.

5. The branch instruction prediction mechanism as claimed in claim 1 wherein each branch set entry comprises four branch instruction entries.

6. The branch instruction prediction mechanism as claimed in claim 1 wherein each branch set entry further comprises a branch pattern table.

7. The branch instruction prediction mechanism as claimed in claim 1 wherein each said branch instruction entry in said branch target buffer cache comprises:

a tag address field;

a branch target address; and

a valid bit.

8. The branch instruction prediction mechanism as claimed in claim 7 wherein said tag address field comprises a compressed tag address field that is smaller than a full tag address.

9. The branch instruction prediction mechanism as claimed in claim 7 wherein said a compressed tag address field comprises a subset of most significant bits from said full tag address concatenated with a subset of least significant bits from said full tag address.

10. The branch instruction prediction mechanism as claimed in claim 7 wherein said a compressed tag address field comprises a first subset of most significant bits from said full tag address, an exclusive or combination of a second subset of bits from said full tag address, and a third subset of least significant bits from said full tag address.

11. The branch instruction prediction mechanism as claimed in claim 7 wherein each said branch instruction entry in said branch target buffer cache further comprises a branch type field.

12. The branch instruction prediction mechanism as claimed in claim 11 wherein each said branch instruction entry in said branch target buffer cache further comprises a block offset field that identifies an offset of a last byte of said associated branch instruction.

13. The branch instruction prediction mechanism as claimed in claim 12 wherein each said branch instruction entry in said branch target buffer cache further comprises a branch history field.

14. The branch instruction prediction mechanism as claimed in claim 13 wherein each said branch instruction entry in said branch target buffer cache further comprises a speculation bit and a speculative branch history field.

15. A method of updating a branch target buffer cache, said method comprising the steps of:

executing a branch instruction to determine a final branch outcome and a final branch target address for said branch instruction;

finding a branch set entry in said branch target buffer cache by indexing into said branch target buffer using an address of a last byte of said branch instruction;

finding a branch instruction entry associated with said branch instruction in said branch set entry;

updating a branch target address in said branch instruction entry associated with said branch instruction using said final branch target address;

updating a branch pattern table associated with said branch set entry in said branch target buffer if said branch instruction is a conditional branch instruction;

updating a branch history associated with said branch instruction entry if said branch instruction is a conditional branch instruction;

matching a subset of most significant bits from said address of a last byte of said branch instruction with a tag field in said branch entry.

16. The method of updating a branch target buffer cache as claimed in claim 15 wherein said step of matching a subset of most significant bits from said address of a last byte of said branch instruction further comprises

generating a hashed version of said subset of most significant bits from said address of a last byte of said branch instruction;

and

matching said hashed version of said subset of most significant bits from said address of a last byte of said branch instruction with a hashed tag field in said branch entry.

17. A method of creating a branch instruction entry in a branch target buffer cache to store information about a discovered branch instruction, said branch target buffer cache organized into a plurality of branch set entries, each branch set entry comprising a set of branch instruction entries, said method comprising the steps of:

executing said discovered branch instruction to determine a final branch outcome and a final branch target address for said discovered branch instruction;

determining if said discovered branch instruction was mispredicted by comparing said final branch outcome and said final branch target address to a predicted branch outcome and a predicted branch target address;

allocating a branch instruction entry in said branch target buffer cache if said discovered branch instruction was mispredicted or if said final branch outcome of said discovered branch instruction was taken, said step of allocating a branch instruction entry comprising the substeps of;

reading a least recently replaced value from a least recently replaced field associated branch set entry;

replacing a branch instruction entry indicated by said least recently replaced value if said first branch entry does not have a matching tag address field;

incrementing said least recently replaced value and repeating said step until all branch instruction entries have been examined if said branch entry has a matching tag address field; and

replacing a branch instruction entry pointed to by said least recently replaced value as originally read from said least recently replaced field if all branch instruction entries have matching tag address fields.