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Method and apparatus for implementing a set-associative branch target buffer

  • US 5,574,871 A
  • Filed: 01/04/1994
  • Issued: 11/12/1996
  • Est. Priority Date: 01/04/1994
  • Status: Expired due to Term
First Claim
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1. A branch instruction prediction mechanism, said branch instruction prediction mechanism predicting a plurality of branch instructions within a stream of computer instructions, said branch instruction prediction mechanism comprising:

  • an instruction pointer for identifying an instruction address in a memory, said instruction pointer having a set of branch target buffer set address bits and a set of branch target buffer tag address bits;

    a branch target buffer cache, said branch target buffer cache comprising a plurality of branch set entries, each of said branch set entries comprising a set of branch instruction entries, each branch instruction entry storing information about an associated branch instruction including a position with a memory block, all branch instruction entries within a particular branch set entry storing branch instructions having identical branch target buffer set address bits; and

    a branch target buffer circuit, said branch target buffer circuit receiving said instruction pointer, said branch target buffer circuit indexing into said branch target buffer cache with said set of branch target buffer set address bits of said instruction pointer to select a branch set entry, said branch target buffer circuit selecting at least one branch instruction entry in said branch set entry using said branch target buffer tag address bits of said instruction pointer.

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