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RISC architecture computer configured for emulation of the instruction set of a target computer

  • US 5,574,927 A
  • Filed: 03/25/1994
  • Issued: 11/12/1996
  • Est. Priority Date: 03/25/1994
  • Status: Expired due to Term
First Claim
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1. A method for emulating the instruction set of a target computer on a RISC architecture computer, comprising the steps of:

  • 1) fetching a target instruction of a format compatible with the instruction set of the target computer;

    2) parsing and decoding said instruction into fields designating an opcode and operands;

    3) converting said opcode into an address pointing to a sequence of one or more microcoded instructions;

    4) decoding said microcoded instruction into a LHS instruction having fields essentially compatible with a RISC architecture and a RHS instruction having fields to select a plurality of indirect registers pointing to emulated registers;

    5) processing said emulated registers with an arithmetic logic unit;

    6) calculating a condition code as a function of the operation of said arithmetic logic unit and a selection field within said microcoded instruction;

    7) storing a result of said processing by said arithmetic logic unit;

    8) storing a result of said condition code calculation; and

    9) repeating steps 4-8 with a next microcoded instruction until an end of said microcoded sequence is encountered and then continuing at step 1 with a next target instruction.

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