RISC architecture computer configured for emulation of the instruction set of a target computer

• US 5,574,927 A
• Filed: 03/25/1994
• Issued: 11/12/1996
• Est. Priority Date: 03/25/1994
• Status: Expired due to Term

• Current Assignee: TechSearch LLC (Acacia Research Corporation)
• Original Assignee: International Meta Systems, Inc.
• Inventors: Scantlin, Henry L.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): DONAGHUE, LARRY D
• Application Number:
  US08/218,225
• Time in Patent Office: 963 Days
• Field of Search: 395/375, 395/500, 395/800
• US Class Current: 712/41
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

A RISC architecture computer configured for emulating the instruction set of a target computer to execute software written for the target computer, e.g., an Intel 80X86, a Motorola 680X0 or a MIPS R3000. The apparatus is integrated with a core RISC computer to form a RISC computer that executes an expanded RISC instruction. The expanded RISC instruction contains data fields which designate indirect registers that point to emulation registers that correspond to registers in the target computer. The width of the emulation registers is at least the width of those in the target computer. However, a field in the expanded RISC instruction restricts the emulated width to that required by a particular emulated instruction. Additionally, the expanded RISC instruction contains a field which designates the emulation mode for condition codes and selects logic to match the condition codes of the target computer. Target instructions are parsed and dispatched to sequences of one or more expanded RISC instructions to emulate each target instruction.

Claims

1. A method for emulating the instruction set of a target computer on a RISC architecture computer, comprising the steps of:

1) fetching a target instruction of a format compatible with the instruction set of the target computer;

2) parsing and decoding said instruction into fields designating an opcode and operands;

3) converting said opcode into an address pointing to a sequence of one or more microcoded instructions;

4) decoding said microcoded instruction into a LHS instruction having fields essentially compatible with a RISC architecture and a RHS instruction having fields to select a plurality of indirect registers pointing to emulated registers;

5) processing said emulated registers with an arithmetic logic unit;

6) calculating a condition code as a function of the operation of said arithmetic logic unit and a selection field within said microcoded instruction;

7) storing a result of said processing by said arithmetic logic unit;

8) storing a result of said condition code calculation; and

9) repeating steps 4-8 with a next microcoded instruction until an end of said microcoded sequence is encountered and then continuing at step 1 with a next target instruction.

2. A method for emulating the instruction set of a target computer on a RISC architecture computer as in claim 1, wherein step 9 additionally comprises detection of single instruction microcode sequence and directly continuing at step 1.

3. The method of claim 2, wherein steps 1-9 occur during a time period comprised of a plurality of clock cycles and step 1 is executed for a next target instruction during each clock cycle.

4. A RISC architecture computer having a native instruction width of N bits configured for emulating target instructions from the instruction set of a target computer, comprising:

a plurality of emulation registers capable of corresponding to registers in the target computer and having data widths greater than or equal to the data widths of the registers in the target computer;

a plurality of indirect registers for selection of said emulation registers;

parsing means to extract a plurality of data fields from a target instruction, at least one said field including an opcode;

dispatching means using said opcode to direct the RISC architecture computer to select at least one M+N bit expanded RISC instruction from a microcode memory;

an expanded instruction decoder for using said M bits from each said expanded RISC instruction to redefine the RISC architecture computer in terms of the target computer, wherein said M bits define fields, said fields comprising a width field for designating the data width of said emulation registers and the data width of an arithmetic function, an indirect register field for designating said indirect registers, and a condition code field for designating a condition code emulation mode; and

condition code calculation means for determining the condition code for an arithmetic function according to said condition code field.

5. The computer of claim 4, wherein said RISC architecture computer and said microcode memory are contained within a single chip and said microcode memory is in ROM.

6. The computer of claim 4, wherein said RISC architecture computer is contained within a single chip and said microcode memory is external to said single chip.

7. The computer of claim 6, wherein said external microcode memory is in RAM.

8. The computer of claim 6, wherein said external microcode memory is in ROM.

9. The computer of claim 4, wherein said target computer is the Intel 80X86.

10. The computer of claim 4, wherein said target computer is the Motorola 680X0.

11. The computer of claim 4, wherein said target computer is the MIPS R3000.

12. The computer of claim 4, additionally comprising means to execute native RISC instructions.

13. The computer of claim 4, wherein said instruction set is comprised of binary combinations of data bits from the instruction set of the target computer, said computer additionally comprising means to execute a sequence of microcoded instructions in response to encountering at least one binary combination of data bits not otherwise within the instruction set of the target computer.

14. A RISC architecture computer having a native instruction width of N bits configured for emulating target instructions from the instruction set of a target computer, comprising:

a plurality of emulation registers capable of corresponding to registers in the target computer and having data widths greater than or equal to the data widths of the registers in the target computer;

a plurality of indirect registers for selection of said emulation registers;

parsing means to extract a plurality of data fields from a target instruction, at least one said field including an opcode;

dispatching means using said opcode to direct the RISC architecture computer to select at least one M+N bit expanded RISC instruction from a microcode memory;

an expanded instruction decoder for using said M bits from each said expanded RISC instruction to redefine the RISC architecture computer in terms of the target computer; and

condition code calculation means for determining the condition code for an arithmetic function in accordance with the target computer.

15. The computer of claim 14, wherein said redefining means comprises using said M bits to define fields, said fields comprising a width field for designating the data width of said emulation registers and the data width of an arithmetic function, and an indirect register field for designating said indirect registers.

16. The computer of claim 14, wherein said expanded instruction decoder uses a condition code field within said M bits for designating a condition code emulation mode;

and

said condition code calculation means is comprised of a plurality of condition code calculators corresponding to a plurality of target computers wherein said condition code field enables one of said plurality of condition code calculators.

17. The computer of claim 14, wherein said RISC architecture computer and said microcode memory are contained within a single chip and said microcode memory is in ROM.

18. The computer of claim 14, wherein said RISC architecture computer is contained within a single chip and said microcode memory is external to said single chip.

19. The computer of claim 18, wherein said external microcode memory is in RAM.

20. The computer of claim 18, wherein said external microcode memory is in ROM.

21. The computer of claim 14, wherein said target computer is the Intel 80X86.

22. The computer of claim 14, wherein said target computer is the Motorola 680X0.

23. The computer of claim 14, wherein said target computer is the MIPS R3000.

24. The computer of claim 14, additionally comprising means to execute native RISC instructions.

25. The computer of claim 14, wherein said instruction set is comprised of binary combinations of data bits from the instruction set of the target computer, said computer additionally comprising means to execute a sequence of microcoded instructions in response to encountering at least one binary combination of data bits not otherwise within the instruction set of the target computer.