Computer system and method using functional memory

• US 5,574,930 A
• Filed: 08/12/1994
• Issued: 11/12/1996
• Est. Priority Date: 08/12/1994
• Status: Expired due to Term

• Current Assignee: University of Hawai'i
• Original Assignee: University of Hawai'i
• Inventors: Lew, Art Y., Halverson, Richard P. Jr.
• Primary Examiner(s): SHAH, ALPESH
• Application Number:
  US08/290,027
• Time in Patent Office: 823 Days
• Field of Search: 395/800, 395/DIG. 1, 395/200.15, 395/311, 395/404, 395/432, 395/438, 395/497.01, 395/800, 395/827, 395/840, 395/843, 395/871, 365/189.01, 365/189.02, 365/189.04, 365/230.01, 365/230.62
• US Class Current: 712/34
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence

Abstract

A computer system has a central processing unit and a functional memory coupled to the central processing unit'"'"'s memory access circuitry. The functional memory includes random access memory circuitry connected in parallel with field programmable gate array circuitry. The field programmable gate array circuitry receives configuration data from the central processing unit. The configuration data defines what memory addresses the field programmable gate array circuitry will be responsive to and what computational functions the field programmable gate array circuitry will perform. The field programmable gate array circuitry includes input registers for storing data received from the central processing unit when the central processing unit'"'"'s memory access circuitry asserts a first set of memory addresses defined by the configuration data and result output circuitry for communicating the results computed by the field programmable gate array circuitry. The result output circuitry outputs result data to the central processing unit when the central processing unit'"'"'s memory access circuitry asserts a second set of memory addresses defined by the configuration data. The functional memory includes access circuitry for routing data signals from the central processing unit to both the random access memory circuitry and the field programmable gate array circuitry in parallel, and for routing data signals from both the random access memory circuitry and the field programmable gate array circuitry to the central processing unit. The field programmable gate array circuitry can be reprogrammed to support different computations for different programs.

Claims

1. A computer system comprising:

a central processing unit, including memory access circuitry for asserting memory addresses and for writing and reading data to and from memory devices at asserted memory addresses;

a functional memory coupled to the central processing unit'"'"'s memory access circuitry, said functional memory including random access memory circuitry connected in parallel with field programmable gate array circuitry;

said field programmable gate array circuitry coupled to said central processing unit so as to receive configuration data for configuring said field programmable gate array circuitry from said central processing unit, said configuration data defining what memory addresses said field programmable gate array circuitry will be responsive to and what computation functions said field programmable gate array circuitry will perform;

said field programmable gate array circuitry including input registers for storing data received from said central processing unit when said central processing unit'"'"'s memory access circuitry asserts a first set of memory addresses defined by said configuration data and result output circuitry for communicating the results computed by said field programmable gate array circuitry, said result output circuitry outputting result data to said central processing unit when said central processing unit'"'"'s memory access circuitry asserts a second set of memory addresses defined by said configuration data; and

said functional memory including access circuitry for routing data signals from said central processing unit to both said random access memory circuitry and said field programmable gate array circuitry in parallel, and for routing data signals from both said random access memory circuitry and said field programmable gate array circuitry to said central processing unit.

2. The computer system of claim 1 wherein said functional memory includes a multiplexer for selectively receiving data from said field programmable gate array circuitry and from said random access memory circuitry.

3. The computer system of claim 1 wherein said functional memory includes logic circuitry for logically ORing data output by said field programmable gate array circuitry and data output by said random access memory circuitry.

4. The computer system of claim 1, wherein

said central processing unit and said field programmable gate array circuitry are programmed to execute a decision table program;

said field programmable gate array circuitry is configured to perform a plurality of computations that include a computation for computing a program address to be used in a program branching instruction to be executed by said central processing unit, said field programmable gate array circuitry configured to output said computed program address when said central processing unit reads a first address in said functional memory;

said central processing unit is programmed (A) to load into input registers in said field programmable gate array circuitry data required as inputs for said plurality of computations performed by said field programmable gate array circuitry, (B) to retrieve said program address computed by said field programmable gate array circuitry by reading said first address in said functional memory, and (C) to jump to said retrieved program address.

5. The computer system of claim 1, wherein

said central processing unit and said field programmable gate array circuitry are programmed to execute a decision table program, said decision table program including a plurality of condition stubs comprising conditions capable of being evaluated as true/false based on specified input data, a set of condition entries for selecting one of a plurality of rules based on evaluations of said condition stubs, action entries comprising a plurality of selectable computations and action stubs for selecting one of said selectable computations to perform based on which of said plurality of rules is selected;

said field programmable gate array circuitry is configured to (A) execute said plurality of condition stubs simultaneously to produce a first set of results, (B) evaluate said set of condition entries using said first set of results used as inputs select one of said plurality of rules, (C) based on said selected rule and said action entries, selecting ones of said action entries, and (D) performing the computations corresponding to said selected action entries;

at least one of said action entries comprises a computation for computing a program address to be used in a program branching instruction to be executed by said central processing unit;

said central processing unit is programmed to (A) load into input registers in said field programmable gate array circuitry data required as inputs to said condition stubs and said action entries programmed into said field programmable gate array circuitry, (B) retrieve said program address computed by said at least one action entry, and (C) jump to said retrieved program address.

6. The computer system of claim 1, further including a system data processor coupled to said central processing unit;

said central processing unit comprising a minimal processor having a plurality of internal registers including a program counter register and at least one other register, said minimal processor further including data processing circuitry that executes only a reduced set of instructions consisting essentially of data move instructions for moving data between said registers in said minimal processor, said random access memory circuitry and said field programmable gate array circuitry, at least one program branching instruction including a program branching instruction for loading said program counter in said minimal processor with an address retrieved from said functional memory, and a program halt instruction for halting instruction execution by said minimal processor;

said minimal processor including circuitry for enabling said system data processor to directly access said random access memory circuitry and said field programmable gate array circuitry so that said system data processor can load programs into said random access memory circuitry for execution by said minimal processor and can load configuration data into said field addressable programmable gate array circuitry.

7. The computer system of claim 6, wherein said functional memory is configured to operate as a spreadsheet computer such that memory locations in said random access memory circuitry and said input registers in said field programmable gate array circuitry store data while memory mapped locations in said field programmable gate array circuitry output expression results computed by said field programmable gate array circuitry as a function of data stored in said input registers.

8. The computer system of claim 6, wherein

said minimal processor and said field programmable gate array circuitry are programmed to execute a decision table program, said decision table program including a plurality of condition stubs comprising conditions capable of being evaluated as true/false based on specified input data, a set of condition entries for selecting one of a plurality of rules based on evaluations of said condition stubs, action entries comprising a plurality of selectable computations and action stubs for selecting one of said selectable computations to perform based on which of said plurality of rules is selected;

said field programmable gate array circuitry is configured to (A) execute said plurality of condition stubs simultaneously to produce a first set of results, (B) evaluate said set of condition entries using said first set of results used as inputs select one of said plurality of rules, (C) based on said selected rule and said action entries, selecting ones of said action entries, and (D) performing the computations corresponding to said selected action entries;

at least one of said action entries comprises a computation for computing a program address to be used in a program branching instruction to be executed by said minimal processor;

said minimal processor is programmed to (A) load into input registers in said field programmable gate array circuitry data required as inputs to said condition stubs and said action entries programmed into said field programmable gate array circuitry, (B) retrieve said program address computed by said at least one action entry, and (C) jump to said retrieved program address.

9. The computer system of claim 1, said central processing unit comprising a minimal processor further including data processing circuitry that executes only a reduced set of instructions consisting essentially of data move instructions for moving data between said registers in said minimal processor, said random access memory circuitry and said field programmable gate array circuitry, at least one program branching instruction including a program branching instruction for loading said program counter in said minimal processor with an address retrieved from said functional memory, and a program halt instruction for halting instruction execution by said minimal processor.

10. The computer system of claim 9, wherein said functional memory is configured to operate as a spreadsheet computer such that memory locations in said random access memory circuitry and said input registers in said field programmable gate array circuitry store data while memory mapped locations in said field programmable gate array circuitry output expression results computed by said field programmable gate array circuitry as a function of data stored in said input registers.

11. The computer system of claim 9, wherein

said minimal processor and said field programmable gate array circuitry are programmed to execute a decision table program, said decision table program including a plurality of condition stubs comprising conditions capable of being evaluated as true/false based on specified input data, a set of condition entries for selecting one of a plurality of rules based on evaluations of said condition stubs, action entries comprising a plurality of selectable computations and action stubs for selecting one of said selectable computations to perform based on which of said plurality of rules is selected;

said field programmable gate array circuitry is configured to (A) execute said plurality of condition stubs simultaneously to produce a first set of results, (B) evaluate said set of condition entries using said first set of results used as inputs select one of said plurality of rules, (C) based on said selected rule and said action entries, selecting ones of said action entries, and (D) performing the computations corresponding to said selected action entries;

at least one of said action entries comprises a computation for computing a program address to be used in a program branching instruction to be executed by said minimal processor;

said minimal processor is programmed to load into input registers in said field programmable gate array circuitry data required as inputs to said condition stubs and said action entries programmed into said field programmable gate array circuitry and is programmed to retrieve said program address computed by said at least one action entry and to jump to said retrieved program address.