Method for making circular tubular channels with two silicon wafers

• US 5,575,929 A
• Filed: 06/05/1995
• Issued: 11/19/1996
• Est. Priority Date: 06/05/1995
• Status: Expired due to Term

• Current Assignee: Lawrence Livermore National Security LLC (Government of the United States of America)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Hui, Wing C., Yu, Conrad M.
• Primary Examiner(s): Breneman, R. Bruce
• Assistant Examiner(s): Goudreau, George A.
• Application Number:
  US08/464,020
• Time in Patent Office: 533 Days
• Field of Search: 156/647.1, 216/8, 216/33, 216/56, 216/99, 216/10
• US Class Current: 216/10
• CPC Class Codes: G01N 30/6052 body
• CPC Class Codes: G01N 30/6095 Micromachined or nanomachined, e.g. micro- or nanosize

Abstract

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si₃ N₄) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO₃ /CH₃ COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

Claims

1. A method for making circular tubular channels with two silicon wafers, comprising:

coating a first surface of a first silicon wafer with a first protective coating resistant to etching;

coating a second surface of a second silicon wafer with a second protective coating resistant to etching;

patterning a first slit entry in said first protective coating along a narrow path defined for a wider tubular channel in said first surface of said first silicon wafer;

patterning a second slit entry, which is a mirror-image of said first slit entry, in said second protective coating along said narrow path defined for said tubular channel in said second surface of said second silicon wafer;

isotropically etching said first and second surfaces of said first and second silicon wafers through said first and second slit entries such that said first and second silicon wafer are eroded equally in all directions from said slit entries, wherein respective halves of said tubular channel are formed, each having a semicircular cross section; and

joining together said first and second silicon wafers at said first and second surfaces with said respective halves of said tubular channel aligned to produce an overall circular cross section for said tubular channel.

2. The method of claim 1, further comprising before the step of joining:

etching an alignment means into said first and second silicon wafers for precision matching of two parts of said tubular channel providing for after the step of joining a whole tubular channel that has a round cross section.

3. The method of claim 2, wherein:

the etching of said alignment means provides for a visual alignment window disposed in said first silicon wafer having a through hole and a corresponding visual alignment target disposed in said second silicon wafer having a depression, wherein said through hole and said depression, when coaxially aligned, visually signal a correct microscopic alignment of said first and second silicon wafers.

4. The method of claim 2, wherein:

the etching of said alignment means provides for a first vertical alignment hole in said first silicon wafer and a corresponding second vertical alignment hole in said second silicon wafer; and

further providing a step for forming a pin disposed in said first and second vertical alignment holes for physically-forcing a microscopic alignment of said first and second silicon wafers.

5. The method of claim 2, wherein:

the etching of said alignment means provides for an alignment cavity in said first silicon wafer and a corresponding alignment post in said second silicon wafer for physically-forcing a microscopic alignment of said first and second silicon wafers.

6. The method of claim 2, wherein:

the etching of said alignment means provides for a first and a second vertical alignment hole in said first silicon wafer and a corresponding pair of third and fourth vertical alignment holes in said second silicon wafer, and a pair of loose-fitting pins each simultaneously disposed in said first and third vertical alignment holes and said second and fourth alignment holes provide for physically-forcing a microscopic alignment of said first and second silicon wafers when said pins are pulled apart from one another.

7. The method of claim 6, wherein:

the etching of said alignment means is such that said first through fourth vertical alignment holes are rectangular in plan view and have walls which narrow toward said bonding surfaces, and said pair of loose-fitting pins are each cylindrical in shape, wherein a two-point contact is made with each of said first through fourth vertical alignment holes.