Process for fabricating static random access memory having stacked transistors

• US 5,576,238 A
• Filed: 06/15/1995
• Issued: 11/19/1996
• Est. Priority Date: 06/15/1995
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Fu, Chien-Chih
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US08/490,787
• Time in Patent Office: 523 Days
• Field of Search: 437/47, 437/48, 437/52, 437/918, 437/915, 257/903-904
• US Class Current: 438/152
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/15 comprising a resistor load element

Abstract

A process for fabricating memory cells of a static random access memory (SRAM) device is disclosed to reduce the required die area and increase storage capacity. Each of the memory cells of the SRAM comprises a group of four MOS transistors, a pair of resistors, a pair of bit lines, as well as a word line. The process of fabrication the memory cells of the SRAM device comprises a number of process steps that are implemented subsequently on the surface of said semiconductor substrate, with the first and second MOS transistors first formed on the semiconductor substrate. According to the process, the first and second resistors are then formed on top of the first and second MOS transistors. Then the third and fourth MOS transistors and a word line are subsequently formed on top of the first and second resistors. Finally, the first and second bit lines for the memory cells are formed on top of the third and fourth MOS transistors. The process for fabricating the memory cells is characterized by the fact that the third and fourth MOS transistors are fabricated as vertical conduction transistors having their drains, sources and gates aligned substantially in a direction orthogonal to the plane of the semiconductor substrate.

Claims

1. A process for fabricating memory cells of a static random access memory (SRAM) device having a plurality of memory cells formed on a semiconductor substrate, each of said SRAM memory cells includes:

a first MOS transistor having one of a drain/source pair thereof coupled to a first voltage for said SRAM device;

a second MOS transistor having one of the drain/source pair thereof coupled to said first voltage, the other of the drain/source pair thereof being coupled to the gate of said first MOS transistor and forming a second node, and the gate of said second MOS transistor being coupled to the other of said drain/source pair of said first MOS transistor and forming a first node;

a first resistor coupled to said first node at one end and to a second voltage at the other;

a second resistor coupled to said second node at one end and to said second voltage at the other;

a third MOS transistor having drain/source pair coupled to said first node and a first bit line, and a gate thereof coupled to a word line, respectively; and

a fourth MOS transistor having a pair of drain/source coupled to said second node and a second bit line, and gate thereof coupled to said word line, respectively;

wherein said process comprises;

forming said first and second MOS transistors on said semiconductor substrate;

forming said first and second resistors over said first and second MOS transistors, respectively;

forming said third and fourth MOS transistors and said word line over said first and second resistors, and

forming said first and second bit lines over said third and fourth MOS transistors, respectively.

2. The process for fabricating memory cells of SRAM device of claim 1, wherein each of said third and fourth MOS transistors is fabricated as a vertical conduction transistor having the drain, source and gate thereof aligned substantially in a direction orthogonal to a plane of said semiconductor substrate.

3. The process for fabricating memory cells of SRAM device of claim 2, wherein said word line is utilized as the gates of both of said third and fourth MOS transistors.

4. The process for fabricating memory cells of the SRAM device of claims 3, wherein said gates of each of said first, second, third and fourth MOS transistors and said first and second resistors are formed of polysilicon.

5. The process for fabricating memory cells of SRAM device of claim 1, wherein each of said third and fourth MOS transistors is fabricated as a plane conduction transistor having the drain, source and gate thereof aligned substantially in a direction parallel to the plane of said semiconductor substrate.

6. The process for fabricating memory cells of SRAM device of claim 5, wherein said word line is utilized as the gates of both of said third and fourth MOS transistors.

7. The process for fabricating memory cells of the SRAM device of claim 6, wherein said third and fourth MOS transistors are formed on top of said word line.

8. The process for fabricating memory cells of the SRAM device of claims 7, wherein said gates of each of said first, second, third and fourth MOS transistors and said first and second resistors are formed of polysilicon.

9. The process for fabricating memory cells of the SRAM device of claim 6, wherein said word line is formed on top of said third and fourth MOS transistors.

10. The process for fabricating memory cells of the SRAM device of claims 9, wherein said gates of each of said first, second, third and fourth MOS transistors and said first and second resistors are formed of polysilicon.

11. The process for fabricating memory cells of the SRAM device of claim 1, wherein said first and second MOS transistors are connected to said first and second resistors via contact windows.

12. The process for fabricating memory cells of the SRAM device of claim 1, wherein said first and second resistors are connected to said third and four MOS transistors via contact windows.