Method of making vertical current flow field effect transistor

• US 5,576,245 A
• Filed: 11/18/1992
• Issued: 11/19/1996
• Est. Priority Date: 10/08/1987
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Cogan, Adrian I., Blanchard, Richard A.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US07/978,201
• Time in Patent Office: 1,462 Days
• Field of Search: 437/67, 437/203, 437/919, 437/40, 437/979, 257/302, 257/330, 257/332, 257/333
• US Class Current: 438/270
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/739 controlled by field-effect, e.g. bipolar static induction transistors [BSIT] unijunction transistors H01L29/705
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

A transistor constructed in accordance with our invention includes an N+ substrate, an N- region formed on the N+ substrate, a P- body region formed on the N- region, and an N+ source region formed on the P- body region. A vertical groove extends through the N+, P- and N- regions, and an insulating layer is formed on the groove walls. A polysilicon gate is formed inside the groove. Of importance, the portion of the insulating layer between the polysilicon and the N+ region and the insulating layer between the polysilicon and the N+ substrate is thicker than the portion of the insulating layer between the polysilicon gate and the P- body region. Because of the enhanced thickness of the portions of the .insulating layer between the gate and N+ substrate, the transistor constructed in accordance with our invention is less susceptible to premature field induced breakdown.

Claims

1. A method for making a transistor comprising the steps of:

providing a first semiconductor region of a first conductivity type;

providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than the dopant concentration of said first region;

forming a first groove in said second region;

extending said first groove to at least said first region;

forming a first insulator on the bottom but not on the sidewalls of said first groove;

forming a second insulator over the bottom and sidewalls of said first groove; and

forming a first conductor in said groove.

2. The method of claim 1 wherein the first conductor comprises a gate of said transistor.

3. The method of claim 1 wherein the first semiconductor region comprises a source/drain region of said transistor, and the second semiconductor region comprises a source/drain region of said transistor.

4. A method for making a transistor comprising the steps of:

providing a first semiconductor region of a first conductivity type;

providing a second semiconductor region of said first conductivity type on said first region, said second region having a dopant concentration less than the dopant concentration of said first region;

providing on the second region a third semiconductor region of a second conductivity type opposite to the first conductivity type;

providing a fourth semiconductor region of the first conductivity type on the third region;

forming a groove in said fourth, third and second regions;

extending said groove to at least said first region;

forming a first insulator on the bottom but not on the sidewalls of said groove;

forming a second insulator over the bottom and sidewalls of said groove; and

forming a conductor in said groove.

5. The method of claim 4 wherein the conductor comprises a gate of said transistor.

6. The method of claim 4 wherein the first semiconductor region comprises a source/drain region of said transistor, and the fourth semiconductor region comprises a source/drain region of said transistor.