Fast edge triggered self-resetting CMOS receiver with parallel L1/L2 (master/slave) latch

• US 5,576,644 A
• Filed: 06/02/1995
• Issued: 11/19/1996
• Est. Priority Date: 06/10/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pelella, Antonio R.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Lam, T.
• Application Number:
  US08/459,874
• Time in Patent Office: 536 Days
• Field of Search: 327/51-57, 327/206, 327/208, 327/212, 327/215, 327/198-203, 365/189.05, 365/189.07, 365/207
• US Class Current: 327/51
• CPC Class Codes: H03K 3/356026 with synchronous operation H03K3/356034, H03K3/356052 take precedence
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence

Abstract

A high speed self-resetting, edge-triggered CMOS (SRCMOS) receiver and parallel L1/L2 latch combination are provided which may be used to receive and latch data from a single-ended input of static random access memory (SRAM) or a dynamic random access memory (DRAM). The invention comprises a true/complement generator circuit (TCG) for generating a data and its complement from a single-ended input, a reset circuit for automatically resetting the TCG independent of the system clock, and a parallel L1/L2 latch for storing the data for further processing. The L1/L2 latch preferably has scan-in and scan-out ports useful for testing and diagnostic purposes.

Claims

1. A method for receiving and generating full logic level true and complement data from a single-ended input signal, comprising the steps of:

receiving an input signal into a first input port on the rising edge of a clock pulse;

generating a voltage differential with a complementary current switch to create a true and a complement data signal for said input signal;

amplifying said true and said complement data signals to full logic levels at an output port;

generating a disable signal to disable said first input port;

generating a first reset signal from said true and complement data signals to reset said first input port; and

generating a second reset signal from said true and complement data signals to reset said output port.

2. A method for receiving and generating full logic level true and complement data as recited in claims 1, further comprising the steps of:

receiving true and complement data from a L1/L2 latch into a second input port; and

selecting said first or said second input port to drive said output port.

3. A method for receiving and generating full logic level true and complement data from single-ended input signal as recited in claim 2 further comprising the step of holding said true and complement data in said L1/L2 latch throughout the generation of said first reset signal and said second reset signal.

4. A method for receiving and generating full logic level true and complement data from single-ended input signal as recited in claim 2 further comprising the step of holding a data in an L2 portion of said L1/L2 latch when a new data is stored in an L1 portion of said L1/L2 latch.

5. A method for receiving and generating full logic level true and complement data from single-ended input signal as recited in claim 3 wherein said true and complement data is secured in said L1/L2 latch upon said first input port receiving said first reset signal.

6. A method for receiving and generating full logic level true and complement data from single-ended input signal as recited in claim 4, wherein said data held in said L2 portion is undisturbed when said new data is stored in said L1 portion.

7. A method for receiving and generating full logic level true and complement data from single-ended input signal as recited in claim 1, wherein said step of amplifying is performed devoid of a reference voltage.