Charge pump for phase lock loop
First Claim
Patent Images
1. A charge pump comprising:
- a first high speed switching driver having an output for providing an output signal having a voltage that rapidly swings up or down responsive to an up control signal;
a second high speed switching driver having an output for providing an output signal having a voltage that rapidly swings up or down responsive to a down control signal;
a first transistor of a first type having a drain, having a gate coupled to a first voltage bias line, and having a source coupled to the first high speed switching driver; and
a second transistor of a second type having a drain coupled to the drain of the first transistor of the first type to form an output of the charge pump, having a gate coupled to a second voltage bias line, and having a source coupled to the second high speed switching driver.
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Abstract
A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL also useful for clock synchronizing applications, such as clock recovery elements in transmission/recording channels. The PLL provides in-phase and quadrature signals from a VCO which has two differential transconductor stages having negative output conductance. The PLL also includes a charge pump using transistors driven by high speed switching drivers.
90 Citations
3 Claims
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1. A charge pump comprising:
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a first high speed switching driver having an output for providing an output signal having a voltage that rapidly swings up or down responsive to an up control signal; a second high speed switching driver having an output for providing an output signal having a voltage that rapidly swings up or down responsive to a down control signal; a first transistor of a first type having a drain, having a gate coupled to a first voltage bias line, and having a source coupled to the first high speed switching driver; and a second transistor of a second type having a drain coupled to the drain of the first transistor of the first type to form an output of the charge pump, having a gate coupled to a second voltage bias line, and having a source coupled to the second high speed switching driver. - View Dependent Claims (2)
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3. A uni-directional charge pump comprising:
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a high speed switching driver having an output for providing an output signal having a voltage that rapidly swings up or down responsive to an input control signal; and a transistor having a drain coupled to the output of the charge pump, having a gate coupled to a voltage bias line, and having a source coupled to the high speed switching driver.
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Specification