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Fractional-N frequency synthesizer with temperature compensation

  • US 5,576,666 A
  • Filed: 11/12/1993
  • Issued: 11/19/1996
  • Est. Priority Date: 11/12/1993
  • Status: Expired due to Fees
First Claim
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1. A temperature compensated fractional-N phase locked loop, which synthesizes a desired output frequency from a given reference frequency, by using fractional division ratios, comprising:

  • a phase detector, which compares a phase of the reference frequency with a phase of a feedback frequency, and outputs an oscillator steering signal indicative of a difference therebetween;

    a voltage controlled oscillator, which produces said desired output frequency based at least partly on said oscillator steering signal;

    a programmable divider, receiving said frequency from said voltage controlled oscillator, and dividing said frequency by a dividing ratio, determined from at least two dividing ratios based on a dividing control signal and whose average dividing value has a fractional portion, to produce at its output said feedback frequency;

    an accumulator, which controls said fractional portion of said programmable divider'"'"'s average dividing ratio via said dividing control signal and whose state indicates an error caused by a difference between a current dividing ratio and a desired average dividing ratio, with said error modulating said oscillator steering signal, causing an unwanted spur in an output frequency spectrum of said voltage control oscillator,said phase detector including;

    a phase detector gain adjustment port,a phase detector gain adjustment network attached to said gain adjustment port that at least partially determines a gain of said phase detector,a spur cancellation gain adjustment port,a spur cancellation gain network attached to said spur cancellation port,a spur cancellation circuit to which said spur cancellation gain adjustment port is coupled and receiving from said accumulator a signal indicative of said error and using said signal indicative of error to reduce said spur caused by said error by

         1) amplifying said signal indicative of error using a spur cancellation gain element by an amount dependent on values of components of said spur cancellation gain network, and by

         2) combining said amplified signal indicative of error with said error modulated oscillator steering signal,wherein said spur cancellation gain network includes only non-temperature compensated components therein and said phase detector gain adjustment network includes a temperature compensation component therein to temperature compensate simultaneously a gain of said phase detector gain and said spur cancellation, and where an uncompensated temperature variation in said phase detector gain controlled by said gain adjustment network, has a greater effect on spur level than an uncompensated temperature variation of said spur cancellation gain controlled by said spur cancellation gain network.

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