Fractional-N frequency synthesizer with temperature compensation

• US 5,576,666 A
• Filed: 11/12/1993
• Issued: 11/19/1996
• Est. Priority Date: 11/12/1993
• Status: Expired due to Fees

• Current Assignee: Nippondenso Co., Ltd. (DENSO Corporation)
• Original Assignee: Nippondenso Technical Center USA Incorporated (DENSO Corporation)
• Inventors: Rauvola, Roger
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US08/150,881
• Time in Patent Office: 1,103 Days
• Field of Search: 331/1 R, 331/1 A, 331/66, 331/16, 331/176, 331/25, 331/27, 327/105, 327/107, 327/106, 332/123, 332/124, 332/128
• US Class Current: 331/25
• CPC Class Codes: H03L 1/02 against variations of temperature only
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
• CPC Class Codes: H03L 7/1978 using a cycle or pulse removing circuit

Abstract

A fractional-N frequency synthesizer which incorporates division by a fractional value. Division is by a first value during first cycles and by a second value during second cycles. During the first cycles, an error in value accumulates, and when it reaches a certain value, causes a change in the dividing ratio to reduce the error value. The increase and decrease in error causes spurs in the output frequency spectrum. These spurs are cancelled using a cancellation network. The gain of the phase detector is temperature-compensated and the gain of the spur cancellation network is not, but the temperature compensation of the phase detector gain causes compensation of both values.

Claims

1. A temperature compensated fractional-N phase locked loop, which synthesizes a desired output frequency from a given reference frequency, by using fractional division ratios, comprising:

a phase detector, which compares a phase of the reference frequency with a phase of a feedback frequency, and outputs an oscillator steering signal indicative of a difference therebetween;

a voltage controlled oscillator, which produces said desired output frequency based at least partly on said oscillator steering signal;

a programmable divider, receiving said frequency from said voltage controlled oscillator, and dividing said frequency by a dividing ratio, determined from at least two dividing ratios based on a dividing control signal and whose average dividing value has a fractional portion, to produce at its output said feedback frequency;

an accumulator, which controls said fractional portion of said programmable divider'"'"'s average dividing ratio via said dividing control signal and whose state indicates an error caused by a difference between a current dividing ratio and a desired average dividing ratio, with said error modulating said oscillator steering signal, causing an unwanted spur in an output frequency spectrum of said voltage control oscillator,

said phase detector including;

a phase detector gain adjustment port,

a phase detector gain adjustment network attached to said gain adjustment port that at least partially determines a gain of said phase detector,

a spur cancellation gain adjustment port,

a spur cancellation gain network attached to said spur cancellation port,

a spur cancellation circuit to which said spur cancellation gain adjustment port is coupled and receiving from said accumulator a signal indicative of said error and using said signal indicative of error to reduce said spur caused by said error by

     1) amplifying said signal indicative of error using a spur cancellation gain element by an amount dependent on values of components of said spur cancellation gain network, and by

     2) combining said amplified signal indicative of error with said error modulated oscillator steering signal,

wherein said spur cancellation gain network includes only non-temperature compensated components therein and said phase detector gain adjustment network includes a temperature compensation component therein to temperature compensate simultaneously a gain of said phase detector gain and said spur cancellation, and where an uncompensated temperature variation in said phase detector gain controlled by said gain adjustment network, has a greater effect on spur level than an uncompensated temperature variation of said spur cancellation gain controlled by said spur cancellation gain network.

2. A loop as in claim 1 further comprising a reference frequency generator for generating said reference frequency.

3. A loop as in claim 1 further comprising an integrating loop filter, coupled between said phase detector and said voltage controlled oscillator.

4. A loop as in claim 1 wherein said phase detector includes:

a phase difference detector element which detects a phase difference; and

a first amplifier, which amplifies an output of said phase difference detector element by an amount at least partially dependent on values of components in said phase detector gain adjustment network, and

wherein said spur cancellation circuit includes a spur cancellation amplifier, which receives said signal indicative of said error, and amplifies and inverts a sense of said signal indicative of said error by an amount determined by said spur cancellation gain network attached thereto, and an adder, adding an output of said first amplifier with an output of said spur cancellation amplifier to produce said oscillator steering signal.

5. A loop as in claim 1 wherein said spur cancellation gain network includes only fixed resistors.

6. A loop as in claim 5 wherein said phase detector gain adjustment network includes both fixed resistors and at least one thermistor.

7. A temperature-compensated phase locked loop incorporating a fractional-N type integrated circuit, said loop comprising:

a phase detector receiving a reference frequency at one detection input and a feedback frequency at another detection input and producing an oscillator steering signal indicative of a phase difference therebetween;

a voltage controlled oscillator responsive at least partially to said oscillator steering signal to produce a desired output frequency;

a plurality of components including a temperature compensating component controlling one functional part of said phase locked loop, and which is effective in compensating another functional part of said phase locked loop, wherein an uncompensated temperature variation in said one functional part has a greater effect on an error caused by a difference between a current dividing ratio used to modify said feedback frequency and a desired average dividing ratio than an uncompensated temperature variation of said another functional part;

a programmable divider, receiving said frequency from said voltage controlled oscillator, and dividing said frequency by one of at least two dividing ratios which are chosen based on a dividing control signal and whose average dividing ratio has a fractional portion, to produce at its output said feedback frequency;

an accumulator, which controls said fractional portion of said programmable divider'"'"'s average dividing ratio via said dividing control signal and whose state indicates an error caused by a difference between a current dividing ratio and a desired average dividing ratio, with said error modulating said oscillator steering signal causing an unwanted spur in an output frequency spectrum of said voltage controlled oscillator;

wherein

said phase detector includes a phase detector gain adjustment port and a phase detector gain adjustment network attached thereto that determines at least partially a gain of said phase detector, and a spur cancellation circuit with a spur cancellation gain network attached thereto via a spur cancellation adjustment port, said spur cancellation circuit receiving from said accumulator a signal indicative of said error and using said signal indicative of said error to reduce said spur caused by said error by

     1) amplifying said signal indicative of said error by an amount dependent on values of components in said spur cancellation gain network, and

     2) by combining said amplified signal indicative of error with said error modulated oscillator steering signal;

said phase detector gain adjustment network includes said temperature compensating component therein to temperature compensate a gain of said phase detector; and

said spur cancellation gain network includes only non-temperature compensated components therein,

whereby said spur cancellation is temperature compensated by said phase detector gain adjustment network.

8. A temperature-compensated fractional-N type phase locked loop in which a division operation is performed to divide by one of at least two division ratios resulting in an average division ratio having a fractional portion and in which fractional spur modulation is generated from said division operation, said loop comprising:

a phase detector, receiving a reference frequency at one detection input, and a feedback frequency at another detection input, and producing an oscillator steering signal indicative of a phase difference therebetween;

a voltage controlled oscillator, responsive at least partially to said oscillator steering signal to produce a desired output frequency;

a plurality of components, including a temperature compensating component controlling one functional part of said phase locked loop, and which is effective in compensating another functional part of said phase locked loop, wherein an uncompensated temperature variation in said one functional part has a greater effect on an error caused by a difference between a current dividing ratio used to modify said feedback frequency and a desired average dividing ratio than an uncompensated temperature variation of said another functional part;

a spur cancellation circuit containing a spur cancellation gain element controlled by a spur cancellation gain network; and

a phase detector gain element controlled by a phase detector gain adjustment network;

wherein

said temperature compensating component is provided in said phase detector gain adjustment network and temperature compensates a gain of said phase detector; and

said spur cancellation gain network includes only non-temperature compensated components.

9. A temperature compensated fractional-N phase locked loop, which divides by a desired fractional dividing ratio, comprising:

a phase detector, which compares a phase of a reference frequency with a phase of a feedback frequency, and outputs an error signal indicative of a difference therebetween, said error signal causing undesired phase modulation, said phase detector including a variable gain element controlled by a gain adjustment network attached thereto which amplifies said error signal by an amount at least partially dependent on component values of said gain adjustment network;

a voltage controlled oscillator, which produces a frequency which is based at least partly on said error signal;

a phase modulation cancellation element, with a phase modulation cancellation network attached thereto, receiving a signal indicative of phase error, and using said signal indicative of phase error to compensate for said undesired modulation, by

     1) amplifying said signal indicative of phase error by an amount dependent on values of components in said phase modulation cancellation network, and by

     2) combining said signal indicative of phase error with said error signal,

wherein said gain adjustment network includes a temperature compensation component therein to temperature-compensate a gain of said phase detector, and wherein said phase modulation cancellation network includes only non-temperature compensated components therein, wherein a uncompensated temperature variation in said phase detector has a greater effect on said phase error than an uncompensated temperature variation of a gain of said phase modulation cancellation element whereby said phase modulation cancellation is temperature compensated by said gain adjustment network.

10. A phase locked loop as in claim 9, wherein said phase modulation produces a spur.

11. A method of temperature-compensating a phase locked loop, comprising the steps of:

comparing a phase of a reference frequency with a phase of a feedback frequency to output a difference signal indicative thereof;

multiplying said difference signal by a gain dependent on a first network to produce an amplified difference signal;

temperature compensating said first network;

producing an output frequency based on said amplified difference signal;

cancelling a phase modulation indicative of phase error, using a cancellation circuit controlled by component values of a second network attached thereto, said second network including only non-temperature compensated components, and

temperature compensating said phase modulation cancellation using said temperature compensation of said first network, wherein a temperature variation in a gain of said first network has a greater effect on phase modulation indicative of phase error than a temperature variation of a gain of said second network.

12. A method as in claim 11, wherein said cancelling a phase modulation step is a step of cancelling a spur caused by accumulated error of fractional counting.