Structure and fabrication process of inductors on semiconductor chip

• US 5,576,680 A
• Filed: 03/01/1994
• Issued: 11/19/1996
• Est. Priority Date: 03/01/1994
• Status: Expired due to Term

• Current Assignee: Amer-Soi, Advanced Materials Engineering Research, Inc. (Eurofins Scientific SE)
• Original Assignee: Amer-Soi
• Inventors: Ling, Peiching
• Primary Examiner(s): TSO, LAURA K
• Application Number:
  US08/203,991
• Time in Patent Office: 994 Days
• Field of Search: 336/200, 336/223
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate inductors for integrated circuits H01L28/10
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention discloses an inductive circuit. The inductive circuit is fabricated on a semiconductor chip including a substrate layer and a dielectric layer. The inductive circuit includes an inductive core composed of high magnetic susceptible material (HMSM) surrounded by an dielectric layer. The dielectric layer which surrounds the inductive core is further surrounded by a conductive line which includes the bottom conductive lines the conductive lines in the `vias` through the surrounding dielectric layer and the top conductive lines. The conductive lines are patterned by employing IC fabrication processes. Thus the inductive core, the dielectric layer surrounding the inductive core, and the surrounding conductive line form an inductive circuit and the inductive circuit is formed on the semi-conductor chip which includes the substrate a layer and a dieletric layer.

Claims

1. An integrated-circuit (IC) device includes a plurality of IC circuits integrated on a semiconductor chip, said device comprising:

an inductive circuit including an inductive line formed by connecting a plurality of conductive lines disposed on several layers in said semiconductor chip by utilizing a plurality of lithographically-formed via-connecting lines penetrating between said several layers in said semiconductor chip thus forming an IC inductive coil in said semiconductor chip; and

said inductive line disposed on several layers and said plurality of via-connecting lines are fabricated by lithographic processes on said semiconductor chip wherein said line-widths between said inductive lines and said via-connecting lines being substantially in a submicron range whereby said IC inductive circuit are integratable with said plurality of IC circuits of said IC device in a very large scale integrated (VLSI) circuit and ultra large scale integrated (ULSI) circuit.

2. The IC inductive circuit of claim 1 further comprises:

an inductive core composed of high magnetic susceptible material (HMSM); and

said IC inductive coil is disposed near said inductive core for conducting an inductive electric current therein for generating an inductive magnetic field in said inductive core.

3. The integrated inductive circuit of claim 1 wherein:

said IC inductive coil as being disposed near said inductive core is disposed inside of said inductive core.

4. The integrated inductive circuit of claim 1 wherein:

said IC inductive coil as being disposed near said inductive core is disposed outside of said inductive core.

5. The integrated inductive circuit of claim 3 wherein:

said IC inductive coil as being disposed inside of said inductive core includes a plurality of bottom-inductive lines disposed on a bottom surface of an intermediate layer inside said inductive core, and a plurality of top-inductive lines disposed on the top surface of said intermediate layer; and

said plurality of via-connecting lines further penetrating said intermediate layer for connecting said bottom-inductive lines and said top-inductive lines forming said inductive line surrounding said intermediate layer.

6. The integrated inductive circuit of claim 5 wherein:

said intermediate layer inside said inductive core surrounded by said inductive line is an HMSM layer.

7. The integrated inductive circuit of claim 5 wherein:

said inductive core and said intermediate layer surrounded by said IC inductive coil are both composed of non-conductive HMSM.

8. The integrated inductive circuit of claim 6 wherein:

said inductive core and said intermediate layer surrounded by said IC inductive coil are both composed of conductive HMSM; and

said inductive core and said intermediate layer both are insulated from said IC inductive coil.

9. The integrated inductive circuit of claim 4 wherein:

said IC inductive coil as being disposed outside of said inductive core includes a plurality of bottom-inductive lines disposed on a bottom surface of an HMSM layer forming said inductive core, and a plurality of top-inductive lines disposed on the top surface of said HMSM layer; and

said plurality of via-connecting lines further penetrating said HMSM layer for connecting said bottom-inductive lines and said top-inductive lines forming said IC inductive coil surrounding said HMSM layer forming said inductive core.

10. The integrated inductive circuit of claim 9 wherein:

said inductive core surrounded by said IC inductive coil is composed of a non-conductive HMSM.

11. The integrated inductive circuit of claim 9 wherein:

said inductive core surrounded by said IC inductive coil is composed of a conductive HMSM; and

said inductive core is insulated from said IC inductive coil.

12. The integrated inductive circuit of claim 11 wherein:

said inductive core further includes an insulation layer disposed on said top surface and said bottom surface for insulating said core from said bottom-inductive lines and said top-inductive lines.

16. The IC device of claim 1 further comprising:

an internal circuit and a bonding pad disposed on said semiconductor chip and connected to said inductive coil for protecting said inductive circuits and said plurality of IC circuits from being damaged by electric static discharge (ESD) or electric over stress (EOS).

13. An integrated-circuit (IC) device includes a plurality of IC circuits integrated on a semiconductor chip, said device comprising:

an inductive circuit including an inductive core composed of high magnetic susceptible material (HMSM);

said inductive circuit including at least an IC inductive coil disposed inside of said inductive core for conducting an inductive electric current therein for generating an inductive magnetic field in said inductive core;

said IC inductive coil further including a plurality of bottom-inductive lines disposed on a bottom surface of an intermediate layer inside said inductive core, and a plurality of top-inductive lines disposed on the top surface of said intermediate layer;

said IC inductive coil further includes a plurality of lithographically-formed via-connecting lines penetrating said intermediate layer for connecting said bottom-inductive lines and said top-inductive lines forming said inductive line surrounding said intermediate layer;

said inductive core, said intermediate layer inside said inductive core surrounded by said IC inductive coil, and said IC inductive coil being arranged such that an electric current being prevented from transmitted in said inductive core and said intermediate layer; and

said inductive core and said IC inductive coil being fabricated by IC processes on said IC chip and said inductive line disposed on several layers and said plurality of via-connecting lines are fabricated by lithographic processes on said semiconductor chip wherein said line-widths between said inductive lines and said via-connecting lines being substantially in a submicron range whereby said IC inductive circuit are integratable with said plurality of IC circuits of said IC device in a very large scale integrated (VLSI) circuit and ultra large scale integrated (ULSI) circuit.

14. An integrated-circuit (IC) device includes a plurality of IC circuits integrated on a semiconductor chip, said device comprising:

an inductive circuit including an inductive core composed of high magnetic susceptible material (HMSM);

said inductive circuit including at least an IC inductive coil line disposed outside of said inductive core for conducting an inductive electric current therein for generating an inductive magnetic field in said inductive core;

said IC inductive coil further including a plurality of bottom-inductive lines disposed on a bottom surface of an HMSM layer forming said inductive core, and a plurality of top-inductive lines disposed on the top surface of said HMSM layer;

said IC inductive coil further includes a plurality of lithographically formed via-connecting lines penetrating said HMSM layer for connecting said bottom-inductive lines and said top-inductive lines forming said IC inductive coil surrounding said HMSM layer forming said inductive core;

said inductive core surrounded by said IC inductive coil, and said IC inductive coil being arranged such that an electric current being prevented from transmitted in said inductive core; and

said inductive core and said IC inductive coil being fabricated by IC processes on said IC chip and said inductive line disposed on several layers and said plurality of via-connecting lines are fabricated by lithographic processes on said semiconductor chip wherein said line-widths between said inductive lines and said via-connecting lines being substantially in a submicron range whereby said IC inductive circuit are integratable with said plurality of IC circuits of said IC device in a very large scale integrated (VLSI) circuit and ultra large scale integrated (ULSI) circuit.

15. The integrated inductive circuit of claim 14 wherein:

said inductive core further is composed of a conductive HMSM and includes an insulation layer disposed on said top surface and said bottom surface for insulating said core from said bottom-inductive lines and said top-inductive lines.

17. An integrated-circuit (IC) device includes a plurality of IC circuits integrated on a semiconductor chip, said device comprising:

an inductive circuit including a plurality of inductive coils each formed on a separate horizontal plane in said semiconductor chip;

said inductive circuit including a plurality of lithographically-formed via-connecting lines each penetrating between said horizontal planes for connecting two of said inductive coils thus forming an combined IC inductive coil in said semiconductor chip; and

said inductive coils disposed on several horizontal planes and said plurality of via-connecting lines are fabricated by lithographic processes in said semiconductor chip wherein said line-widths between said inductive coils and said via-connecting lines being substantially in a submicron range whereby said inductive circuit are integratable with said plurality of IC circuits of said IC device in a very large scale integrated (VLSI) circuit and ultra large scale integrated (ULSI) circuit.

18. A method for fabricating an integrated inductive circuit on a semiconductor chip by employing IC fabrication processes comprising the steps of:

(a) applying a lithographic process for patterning a plurality of bottom conductive lines with line widths substantially in a submicron range on said substrate;

(b) forming a medium layer covering said plurality of bottom conductive lines;

(c) applying a lithographic process for patterning a plurality of top conductive lines on top of said medium layer with line widths substantially in said submicron range; and

(d) applying a lithographic process for penetrating a plurality of vias in said submicron range through said medium layer and filling said vias with conductive connecting means for connecting each of said top conductive lines to a corresponding bottom conductive line thus forming a continuous inductive circuit surrounding said medium layer wherein said continuous inductive circuit being fabricated with a size suitable for integration in a very large scale integrated (VLSI) circuit and ultra large scale integrated (ULSI) circuit with a plurality of IC circuits on said semiconductor chip.

19. The method for fabricating said integrated inductive circuit of claim 18 wherein:

said step (b) of forming a medium layer including the steps of

(b1) forming a bottom dielectric layer on top of said bottom plurality of conductive lines;

(b) forming a high magnetic susceptible material (HMSM) layer on top of said bottom dielectric layer; and

(b3) forming a top dielectric layer on top of said HMSM layer whereby said inductive circuit surrounding said medium layer as a core which including a HMSM layer therein.

20. A method for fabricating an integrated inductive circuit on a semiconductor chip by employing IC fabrication processes comprising the steps of:

(a) forming a bottom HMSM layer with a non-conductive HMSM material on top of said substrate;

(b) applying a lithographic process for patterning a plurality of bottom conductive lines with line widths substantially in a submicron range on said bottom HMSM layer;

(c) forming a medium layer covering said plurality of bottom conductive lines;

(d) applying a lithographic process for patterning a plurality of top conductive lines on top of said medium layer with line widths substantially in said submicron range;

(e) applying a lithographic process for penetrating a plurality of vias in said submicron range through said medium layer and filling said vias with conductive connecting means for connecting each of said top conductive lines to a corresponding bottom conductive line thus forming a continuous inductive circuit surrounding said medium layer wherein said continuous inductive circuit being fabricated with a size suitable for integration in a very large scale integrated (VLSI) circuit and ultra large scale integrated (ULSI) circuit with a plurality of IC circuits on said semiconductor chip; and

(f) forming a top HMSM layer with a non-conductive HMSM material on top of said top conductive lines whereby said inductive circuit being surrounded by said bottom and said top HMSM layers.

21. An IC device includes a plurality of IC circuits integrated on a semiconductor chip, said device comprising:

an inductive circuit including an outer inductive-coil circuit including a plurality of outer bottom conductive lines formed on an outer bottom layer and a plurality of outer top conductive lines formed on an outer top layer wherein said outer bottom and outer top conductive lines being formed with line widths substantially in a submicron range;

said inductive circuit including an inner inductive-coil circuit including a plurality of inner bottom conductive lines formed on an inner bottom layer and a plurality of inner top conductive lines formed on an inner top layer wherein said inner bottom and inner top conductive lines being formed with line widths substantially in said submicron range;

said inductive circuit including said inner bottom inner layer being the same as said outer bottom layer;

said inductive circuit including a first medium layer formed on top of said inner bottom layer covering said outer bottom conductive lines and said inner bottom conductive lines and supporting said inner top conductive lines thereon;

said inductive circuit including a second medium layer formed on top of said first medium layer covering said inner top conductive lines and supporting said outer top conductive lines thereon; and

said inductive circuit including a plurality of lithographically-formed outer vias substantially in a submicron range and lithographically-formed inner vias substantially in a submicron range penetrating said first and second medium layers for connecting said outer top and bottom conductive lines in forming an outer inductive coil and for connecting said inner top and bottom conductive lines in forming an outer inductive coil wherein said inner inductive coil being surrounded by said outer inductive coil, wherein said inner and said outer inductive coils being formed with sizes suitable for integration with said plurality of IC circuits of said IC device in a very large scale integrated (VLSI) circuit and ultra large scale integrated (ULSI) circuit.

22. An IC device includes a plurality of IC circuits integrated on a semiconductor chip, said device comprising:

an inductive circuit including an outer inductive-coil circuit including a plurality of outer bottom conductive lines formed on an outer bottom layer and a plurality of outer top conductive lines formed on an outer top layer wherein said outer bottom and outer top conductive lines being formed with line widths substantially in submicron range;

said inductive circuit including an inner inductive-coil circuit including a plurality of inner bottom conductive lines formed on an inner bottom layer and a plurality of inner top conductive lines formed on an inner top layer wherein said inner bottom and inner top conductive lines being formed with line widths substantially in submicron range;

said inductive circuit including a first medium layer formed on top of said outer bottom layer covering said outer bottom conductive lines and supporting said outer bottom conductive lines thereon;

said inductive circuit including a second medium layer formed on top of said first medium layer covering said inner bottom conductive lines and supporting said inner top conductive lines thereon;

said inductive circuit including a third medium layer formed on top of said second medium layer covering said inner top conductive lines and supporting said outer top conductive lines thereon; and

an inductive circuit including a plurality of lithographically-formed outer vias substantially in a submicron range and lithographically-formed inner vias substantially in a submicron range penetrating said first, second and third medium layers for connecting said outer top and bottom conductive lines in forming an outer inductive coil and for connecting said inner top and bottom conductive lines in forming an outer inductive coil wherein said inner inductive coil being surrounded by said outer inductive coil, wherein said inner and said outer inductive coils being formed with sizes suitable for integration with said plurality of IC circuits of said IC device in a very large scale integrated (VLSI) circuit and ultra large scale integrated (ULSI) circuit.

23. The IC device of claim 22 wherein:

said inductive circuit further including a plurality of additional-inner inductive coils formed in parallel to and deposed near said inner inductive coil wherein said additional-inner inductive coils and said inner inductive coil being surrounded by said outer inductive coil therein.