Video decoder

• US 5,576,765 A
• Filed: 03/17/1994
• Issued: 11/19/1996
• Est. Priority Date: 03/17/1994
• Status: Expired due to Term

• Current Assignee: MediaTek, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Phillips, James E., Conzola, Vincent C., Pfeiffer, Richard T., Cheney, Dennis P., Ngai, Chuck H.
• Primary Examiner(s): Chin, Tommy P.
• Assistant Examiner(s): RAO, ANAND SHASHIKANT
• Application Number:
  US08/214,929
• Time in Patent Office: 978 Days
• Field of Search: 348/406, 348/407, 348/409, 348/419, 348/408, 348/416, 348/409, 364/757, 364/758, 364/759, 364/786, 364/787, 364/788
• US Class Current: 375/240.02
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards

Abstract

A digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals includes a FIFO Data Buffer, a RAM having (1) a compressed, encoded Data Buffer and (2) a data portion for storing decompressed digital video buffer data. A Memory Management Unit is provided for managing the RAM. The decoder has a decoder processor that includes a Variable Length Code Decoder for receiving encoded data, a (2,3,3) parallel counter based Inverse Quantizer for dequantizing the decoded data, an Inverse Discrete Cosine Transform Decoder for transforming the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures, a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM, a Display Unit to output motion compensated pictures from the RAM, and a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.

Claims

1. A digital signal decoder system for receiving compressed encoded digital video signals and transmitting decompressed decoded digital video signals, said decoder system comprising:

a. a FIFO Data Buffer;

b. a RAM having (1) a compressed, encoded Data Buffer connected to the FIFO Data Buffer and adapted to receive and store encoded compressed digital video data from the FIFO Data Buffer, and (2) a data portion for storing decompressed digital video data;

c. a Memory Management Unit for managing the RAM;

d. a Variable Length Code Decoder for receiving encoded data from the compressed, encoded Data Buffer portion of the RAM, and providing a decoded bit stream thereof;

e. a (2,3,3) parallel counter Inverse Quantizer having the Boolean representation;

C"=(U NAND V) NAND ((U XOR V) NAND ((X NAND Y) NAND (X NAND Z) NAND (Y NAND Z))),

C'"'"'=(U XOR V) XOR ((X NAND Y) NAND (X NAND Z) NAND (Y NAND Z)) and

S=(X XOR Y) XOR Z, where U, V, X, Y, and Z are inputs to the (2,3,3) parallel counter and C'"'"', C", S are outputs of the (2,3,3) parallel counter,

for dequantizing the decoded data from the variable length decoder;

f. an Inverse Discrete Cosine Transform Decoder for inverting the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures;

g. a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM;

h. a Display Unit to output motion compensated pictures from the RAM; and

i. a Reduced Instruction Set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.

2. A digital signal decoder system for receiving encoded digitized video signals and transmitting decoded digital video signals, said decoder system having a RAM with (1) a compressed, encoded Data Buffer adapted to receive and store encoded compressed digital video data, and (2) a data portion for storing decompressed digital video buffer, a Memory Management Unit for managing the RAM, and an integrated circuit chip comprising:

a. a FIFO Data Buffer;

b. a Variable Length Code Decoder for receiving encoded data from the RAM compressed, encoded Data Buffer, and providing a decoded bit stream thereof;

c. a (2,3,3) parallel counter Inverse Quantizer having the Boolean representation;

C"=(U NAND V) NAND ((U XOR V) NAND ((X NAND Y) NAND (X NAND Z) NAND (Y NAND Z))),

C'"'"'=(U XOR V ) XOR ((x NAND Y) NAND (X NAND Z) NAND (Y NAND Z)), and

S=(X XOR Y) XOR Z, where U, V, X, Y, and Z are inputs to the (2,3,3)parallel counter and C'"'"', C", S are outputs of the (2,3,3) parallel counter,

for dequantizing the decoded data from the variable length decoder;

d. an Inverse Discrete Cosine Transform Decoder for inverting the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures;

e. a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM;

f. a Display Unit to output motion compensated pictures from the RAM; and

g. a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.

3. An integrated circuit chip for a system for receiving encoded digitized video signals and transmitting decoded digital video signals, said system including the integrated circuit chip and a RAM with (1) a compressed, encoded Data Buffer adapted to receive and store encoded compressed digital video data, and (2) a data portion for storing decompressed digital video buffer, a Memory Management Unit for managing the RAM, the integrated circuit chip comprising:

a. a FIFO Data Buffer;

b. a Variable Length Code Decoder for receiving encoded data from the RAM compressed, encoded Data Buffer, and providing a decoded bit stream thereof;

c. a (2,3,3) parallel counter Inverse Quantizer having the Boolean representation;

C"=(U AND V) NAND ((U XOR V) NAND ((X AND Y) NAND (X NAND Z) NAND (Y NAND Z))),

C'"'"'=(U XOR V) XOR ((X AND Y) NAND (X NAND Z) NAND (Y NAND Z)), and

S=(X XOR Y) XOR Z, where U, V, X, Y, and Z are inputs to the (2,3,3) parallel counter and C'"'"', C", S are outputs of the (2,3,3) parallel counter,

for dequantizing the decoded data from the variable length decoder;

d. an Inverse Discrete Cosine Transform Decoder for inverting the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures;

e. a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM;

f. a Display Unit to output motion compensated pictures from the RAM; and

g. a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.

4. A digital entertainment system comprising a digital signal decoder system for receiving encoded digitized video signals and transmitting decoded digital video signals, said decoder system comprising:

a. a FIFO Data Buffer;

b. a RAM having (1) a compressed, encoded Data Buffer connected to the FIFO Data Buffer and adapted to receive and store encoded compressed digital video data therefrom, and (2) a data portion for storing decompressed digital video buffer;

c. a Memory Management Unit for managing the RAM;

d. a Variable Length Code Decoder for receiving encoded data from the RAM compressed, encoded Data Buffer, and providing a decoded bit stream thereof;

e. a (2,3,3) parallel counter Inverse Quantizer having the Boolean representation;

C"=(U NAND V) NAND ((U XOR V) NAND ((X NAND Y) NAND (X NAND Z) NAND (Y NAND Z))),

C'"'"'=(U XOR V) XOR ((X NAND Y) NAND (X NAND Z) NAND (Y NAND Z)), and

S=(X XOR Y) XOR Z, where U, V, X, Y, and Z are inputs to the (2,3,3) parallel counter and C'"'"', C", S are outputs of the (2,3,3) parallel counter,

for dequantizing the decoded data from the variable length decoder;

f. an Inverse Discrete Cosine Transform Decoder for inverting the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures;

g. a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM;

h. a Display Unit to output motion compensated pictures from the RAM;

i. a reduced instruction set Controller to determine the state of the FIFO Data Buffer and to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit;

j. an audio decoder unit; and

k. an output unit chosen from a television set, a recorder, a computer, and a network for rebroadcast.

5. An Inverse Discrete Cosine Transform video decoder having a variable length decoder, an inverse quantizer, and an inverse discrete cosine transform transformer, the improvement wherein the inverse quantizer comprises (2,3,3) parallel counters, each having the Boolean representation

C"=(U NAND V) NAND ((U XOR V) NAND ((NAND Y) NAND (X NAND Z) NAND (Y NAND Z))),

C'"'"'=(U XOR V) XOR ((X NAND Y) NAND (X NAND Z) NAND (Y NAND Z)), and

S=(X XOR 7) XOR Z, where U, V, X, Y, and Z are inputs to the (2,3,3) parallel counter and C'"'"', C", S are outputs of the (2,3,3) parallel counter.