Telecommunications switch architecture

• US 5,576,873 A
• Filed: 05/03/1995
• Issued: 11/19/1996
• Est. Priority Date: 08/01/1992
• Status: Expired due to Fees

• Current Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Original Assignee: Northern Telecom Limited (Nortel Networks Corporation)
• Inventors: Crossland, William A., Sparks, Adrian P., Birch, Martin J., Scarr, Robert W.
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): NEGASH, KINFE MICHAEL
• Application Number:
  US08/379,515
• Time in Patent Office: 566 Days
• Field of Search: 359/109, 359/117, 359/128, 359/139, 364/713, 385/17, 370/58.1, 370/59
• US Class Current: 398/54
• CPC Class Codes: H04J 2203/0012 Switching modules and their interconnections
• CPC Class Codes: H04J 2203/0019 Multicast/broadcast capabilities
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5605 Fibre
• CPC Class Codes: H04L 2012/5682 Threshold; Watermark
• CPC Class Codes: H04L 49/106 using space switching, e.g. crossbar or matrix
• CPC Class Codes: H04L 49/1553 Interconnection of ATM switching modules, e.g. ATM switching fabrics
• CPC Class Codes: H04L 49/1576 Crossbar or matrix
• CPC Class Codes: H04L 49/203 ATM switching fabrics with multicast or broadcast capabilities
• CPC Class Codes: H04L 49/606 Hybrid ATM switches, e.g. ATM&STM, ATM&Frame Relay or ATM&IP
• CPC Class Codes: H04Q 11/0005 Switch and router aspects
• CPC Class Codes: H04Q 11/0066 Provisions for optical burst or packet networks
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections
• CPC Class Codes: H04Q 2011/0011 using wavelength conversion
• CPC Class Codes: H04Q 2011/0013 using gating amplifiers
• CPC Class Codes: H04Q 2011/0022 using fibre gratings
• CPC Class Codes: H04Q 2011/0024 using space switching
• CPC Class Codes: H04Q 2011/0039 Electrical control
• CPC Class Codes: H04Q 2011/0052 Interconnection of switches

Abstract

Telecommunications switch architectures and switching methods based on the principle of replication/broadcasting some or all of the incoming data from each input-switch port to all output switch ports. The replicated data is transferred to the output ports either by the respective output port reading directly from a relevant address in an input memory, or by transferring the content of all or part of the input memory data simultaneously en bloc and in parallel to a plurality of output memories, with each output port then taking the data intended therefor. The input and output data is in serial form but transferred in parallel form. The data can be replicated optically or electronically. In particular, the input data can be formatted as spatially arranged pages in the optical domain by spatial light modulators (SLM) and switched by an image replicating optical switch, such as a matrix-matrix switch, to an output plane at which a second SLM device converts the data back to serial form. The SLM'"'"'s may be based on FELC/VLSI technology. A mixture of ATM and STM data can be switched in a single arrangement.

Claims

1. A switching architecture, including a plurality of incoming links and a plurality of outgoing links, and switch means for switching data between the incoming and outgoing links, which data is in serial form on said incoming links, the architecture further including means for convening said serial data into parallel form and comprising, for each incoming link, address decode and memory write means;

one or more input memory blocks in which said data is stored at specific addresses;

means for replicating the data whereby all incoming data are available for all or selected outgoing links, said converting, storing and replicating means being interconnected whereby the storage occurs before the replication or concurrently therewith and the replication occurs when the data is in serial or parallel form;

means for each replication, for transferring data from one of said memory blocks to the appropriate one of said outgoing links, which transfer means is arranged either to read directly from the relevant address in said input memory blocks or to transfer the content of all or part of said input memory blocks simultaneously en bloc and in parallel to a plurality of output memory blocks, each associated with a respective outgoing link; and

means for each outgoing link for taking the incoming data intended therefor and reading that data out in serial form, wherein there is a respective source memory for each incoming link, the decoded address information being stored in a respective area of the source memory, each of which source memories comprises a said input memory block, wherein means are provided to convert the source memory content to optical form and the replicating means comprises optical replicating means for acting on said optical form of the source memory content, there being a respective destination memory for each said outgoing link, each of which destination memories comprises a said output memory block, a respective read-out means being connected to each said destination memory, each outgoing link being connected to a respective read-out means and the read-out means serving only to read out the memory content intended for that outgoing link as determined from said stored address information, and including central or distributed control means controlling the operation of the address decode and memory write means, the source memories, the destination memories and the read-out means.

2. An architecture as claimed in claim 1, wherein the means for converting said serial data into parallel form and said memory blocks are together such that input data is arranged in a first spatially arranged page plane, and wherein the data arranged in said first plane is replicated optically to said outgoing links and replicating means comprising image replicating optics.

3. An architecture as claimed in claim 2, wherein the replicating means comprises holographic fan-out optics.

4. An architecture as claimed in claim 3, and including a shutter plane disposed between the incoming and outgoing links and serving to cause transfer of said part of the content of the first spatially arranged page plane to the outgoing output links.

5. An architecture as claimed in claim 4, and including fan-in optics disposed between the shutter plane and the outgoing links.

6. An architecture as claimed in claim 4, and including a second spatially arranged page plane disposed in front of said outgoing links and comprising said output memory blocks.

7. An architecture as claimed in claim 3, and wherein the holographic fan-out optics is comprised by a Fourier plane array generator.

8. An architecture as claimed in claim 2, wherein the replicating means is comprised by either a matrix-vector multiplier or a matrix-matrix multiplier.

9. An architecture as claimed in claim 2, wherein the first spatially arranged page plane is comprised by ferro-electric liquid crystal/very large scale integration (FELC/VLSI) on silicon technology.

10. An architecture as claimed in claim 6, wherein the second spatially arranged page plane is comprised by FELC/VLSI on silicon technology which serves also to read the transferred data out in serial form.

11. An architecture as claimed in claim 2, wherein said first spatially arranged plane comprises a page formatter plane including an input whereby incoming serial data is fed to a series of electronic logic units, each having a respective light modulating pad to a corresponding state.

12. An architecture as claimed in claim 11 and including laser means for reading the states of the modulators of the first plane, the replicating means serving to replicate the read states of the modulators and to transfer the information in parallel to said output memory blocks.

13. An architecture as claimed in claim 11 wherein each logic unit includes more than one memory cell whereby to facilitate simultaneous read-in and read-out of data.

14. An architecture as claimed in claim 13 wherein two memory cells which are written and read alternately are associated with each modulator.

15. An architecture as claimed in claim 1 wherein there is the same number of incoming links as there are input memory blocks but the links are not always connected to the same input memory block, the inputs on the incoming links being shuffled whereby to balance the overall input data traffic between the memory blocks.

16. An architecture as claimed in claim 1 and wherein the shuffle is such that the straight-through connections between links and memory blocks, which would pertain if there was no shuffle, are not permitted to occur.

17. An architecture as claimed in claim 16, wherein each plane has optical transmitters and/or receivers whereby control information can be carried optically through the switching architecture.

18. An architecture as claimed in claim 10 wherein the data incoming on each link is applied to all memory blocks via a respective address decode, serial to parallel conversion and memory write unit whereby storage and replication occurs concurrently, and wherein each memory block has a respective read-out unit coupled to a respective outgoing link and which serves to read directly from the relevant address in said input memory block the input data intended for the respective outgoing link.

19. An architecture as claimed in claim 18, and wherein there are the same number of incoming links as there are memory blocks but the links are not always connected to the same memory write units rather the inputs on the incoming links are shuffled therebetween.