Voltage regulator for non-volatile semiconductor memory devices
First Claim
1. A circuit for regulating the voltage applied to a bit line of a floating-gate memory, comprising:
- a voltage divider network connected between a programming voltage connection and chip ground;
an array of floating-gate field effect transistor memory cells organized in bit lines;
said voltage divider network comprising gate elements of said transistors of said array interconnected as resistive voltage divider elements; and
a voltage regulator circuit, connected to drive at least a selected one of said bit lines of said array with a voltage which is determined by that of an intermediate point in said voltage divider.
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Accused Products
Abstract
A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (VPP) and having an input terminal connected to a divider (6) of said programming voltage (VPP) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.
27 Citations
39 Claims
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1. A circuit for regulating the voltage applied to a bit line of a floating-gate memory, comprising:
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a voltage divider network connected between a programming voltage connection and chip ground; an array of floating-gate field effect transistor memory cells organized in bit lines; said voltage divider network comprising gate elements of said transistors of said array interconnected as resistive voltage divider elements; and a voltage regulator circuit, connected to drive at least a selected one of said bit lines of said array with a voltage which is determined by that of an intermediate point in said voltage divider. - View Dependent Claims (2, 3)
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4. A circuit for regulating the voltage applied to a bit line of a floating-gate memory, comprising:
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an array of floating-gate field effect transistor memory cells organized in bit lines; a voltage divider network, connected between a programming voltage connection and chip ground, comprising gate elements of said transistors of said array interconnected as resistive voltage divider elements; and a voltage regulator circuit, connected to drive at least a selected one of said bit lines of said array with a voltage which is equal to that of an intermediate point in said voltage divider. - View Dependent Claims (5, 6)
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7. A nonvolatile memory integrated circuit, comprising:
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an array of floating-gate field effect transistor memory cells, each including a control gate overlying a floating gate which is capacitively coupled to a respective transistor channel, wherein said array is organized in bit lines; a voltage divider comprising elements in the same thin film layer as said control gate, and configured to provide a dividing ratio which is affected by process variations in said thin film layer; and a voltage regulator circuit, connected to drive at least a selected one of the bit lines of said array with a voltage which is equal to that of an intermediate point in said voltage divider; wherein variations in the effective channel length of said memory cells produce corresponding variations in said regulated drain voltage, to provide an optimal regulated drain voltage. - View Dependent Claims (8, 9, 10, 11, 12, 35)
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13. A nonvolatile memory integrated circuit, comprising:
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an array of floating-gate field effect transistor memory cells, each including a control gate overlying a floating gate which is capacitively coupled to a respective transistor channel, wherein said array is organized in bit lines; a voltage divider comprising elements in the same thin film layer as said control gate, and also comprising elements in the same thin film layer as said floating gate, and configured to provide a dividing ratio which is affected by process variations in said thin film layer; and a voltage regulator circuit, connected to drive at least a selected one of the bit lines of said array with a voltage which is equal to that of an intermediate point in said voltage divider; wherein variations in the effective channel length of said memory cells produce corresponding variations in said regulated drain voltage, to provide an optimal regulated drain voltage. - View Dependent Claims (14, 15, 16, 17, 18, 36)
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19. A nonvolatile memory integrated circuit, comprising:
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an array of floating-gate field effect transistor memory cells, each including a control gate overlying a floating gate which is capacitively coupled to a respective transistor channel, wherein said array is organized in bit lines; a voltage divider comprising elements in the same thin film layer as said floating gate, and configured to provide a dividing ratio which is affected by process variations in said thin film layer; and a voltage regulator circuit, connected to drive at least a selected one of the bit lines of said array with a voltage which is equal to that of an intermediate point in said voltage divider; wherein variations in the effective channel length of said memory cells produce corresponding variations in said regulated drain voltage, to provide an optimal regulated drain voltage. - View Dependent Claims (20, 21, 22, 23, 24, 37)
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25. A method for regulating the write voltage applied to bit lines in a memory chip including nonvolatile field-effect transistors, comprising the steps of:
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(a.) generating a voltage at an intermediate node of a voltage divider, which includes at least one resistive element in the same thin film layer as at least one gate element of said nonvolatile field-effect transistors, said voltage divider being connected between a programming voltage connection and chip ground; and (b.) when a bit line is selected for a write operation, using a voltage regulator which references said intermediate node of said voltage divider to apply a constant regulated voltage to said selected bit line; wherein said regulated voltage has little or no dependence on said programming voltage, and is optimized for the variations in the device characteristics of memory cells of the array. - View Dependent Claims (26, 38)
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- 27. A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage supplied by a programming voltage and having an input terminal connected to a divider of said programming voltage and an output terminal connected to a programming line of at least one memory cell, comprising at least one circuit element capable of adapting the programming line voltage on the basis of the length of the memory cell.
Specification