Data processing system and semiconductor memory suited for the same

• US 5,576,997 A
• Filed: 09/20/1994
• Issued: 11/19/1996
• Est. Priority Date: 09/20/1993
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakajima, Kazunori, Masuda, Noboru, Maejima, Hideo
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/309,418
• Time in Patent Office: 791 Days
• Field of Search: 365/154, 365/189.01, 365/189.04, 365/189.05, 365/23.01, 365/230.03
• US Class Current: 365/189.04
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

A data processing system having a logic LSI, a plurality of memory LSIs and a circuit which eliminates delays in the time at which data read out form the memory LSIs reach the logic LSI. The circuit includes variable delay circuits for delaying the data signals read out of the memory LSIs. A control circuit start monitors the time when the data read out of the individual memory LSIs arrive at flip-flops which output the data to the logic LSI. The delay times in the variable delay circuits are controlled by the control circuit for the individual memory LSIs so that the times the data read out from the memory LSIs reach the logic LSI may coincide with a predetermined standard time. Thus, the read data from the individual memory LSIs are caused to reach the flip-flops simultaneously.

Claims

1. A memory data output circuit for outputting data read out from a plurality of memories at substantially the same time in a data processing system which includes a processor, a plurality of memories, an address bus for transmitting an address fed from said processor to said plurality of memories, and a plurality of data buses provided individually for said plurality of memories for transmitting a plurality of data fed from said processor in parallel to said plurality of memories and for transmitting a plurality of data read out of said plurality of memories in parallel to said processor, said memory data output circuit comprising:

a plurality of transmission circuits provided individually for said plurality of memories for transmitting from said plurality of memories via said plurality of data buses to said processor a plurality of data read out of said plurality of memories with adjustable delay times; and

a control circuit which adjusts delay times of said plurality of transmission circuits in response to data output timings of said plurality of transmission circuits at which the plurality of data read out of said plurality of memories are provided by said plurality of transmission circuits.

2. A memory output circuit as set forth in claim 1, wherein said control circuit includes:

a first circuit which feeds a read address to said plurality of memories via said address bus;

a monitor circuit which monitors individual data output timings of said plurality of transmission circuits; and

a second circuit which adjusts the individual delay times of said plurality of transmission circuits in accordance with results of monitoring by said monitor circuit.

3. A memory output circuit as set forth in claim 2, wherein said monitor circuit comprises:

a generator circuit which generates a standard signal indicating a standard timing, at which said plurality of data should reach said processor through said plurality of transmission circuits; and

a third circuit which monitors the data output timings of said plurality of transmission circuits in terms of differences between the data output timings of said plurality of transmission circuits and the standard timing indicated by said standard signal.

4. A memory data output circuit as set forth in claim 3,

wherein said third circuit selectively outputs one of a count up signal and a count down signal to each of said plurality of transmission circuits based upon one of the differences monitored by said monitor circuit for each of said plurality of transmission circuits,

wherein said second circuit includes an UP/DOWN counter responding to said one of said count up signal and said count down signal provided by said monitor circuit for each of said plurality of transmission circuits,

wherein each of said transmission circuits comprises a variable delay circuit for delaying the data read out to the corresponding data bus with a delay time corresponding to a count value of the UP/DOWN counter;

wherein said first circuit feeds a read address at different times so that said third circuit repeats outputting of one of a count up signal and a count down signal for said plurality of transmission circuits.

5. A memory data output circuit as set forth in claim 4,

wherein said control circuit further comprises:

an output circuit which outputs an early signal and a delayed signal, which are shifted by a constant time period from said standard signal, and

wherein said third circuit includes a plurality of circuits each circuit provided for one of said transmission circuits, said each circuit generating a count-up signal or a count-down signal from said standard signal, said early signal, said delayed signal and one of the data outputs by one of said transmission circuits.

6. A memory data output circuit as set forth in claim 2, further comprising:

a plurality of flip-flops for receiving the outputs of said plurality of transmission circuits in response to identical operating clocks of said processor and feeding the received signals to said processor,

wherein said monitor circuit includes a detection circuit which detects the timings of changes of outputs of said flip-flops.

7. A memory data output method of outputting data read out from a plurality of memories at substantially the same time in a data processing system which includes a processor, a plurality of memories, an address bus for transmitting an address fed from said processor to said plurality of memories, and a plurality of data buses provided individually for said plurality of memories for transmitting a plurality of data fed from said processor in parallel to said plurality of memories and transmitting a plurality of data read out of said plurality of memories in parallel to said processor, said memory data output method comprising the steps of:

delaying transmission of a plurality of data, read out of said plurality of memories, to said processor via said plurality of data buses; and

determining individual delay times of said transmission so that the plurality of data read out of said plurality of memories for an identical address fed from said processor may reach said processor at substantially the same time;

wherein said determining step includes the step of;

controlling the delay times of a plurality of transmission circuits for transmitting to said plurality of data buses data from said plurality of memories in response to data output timings of said plurality of transmission circuits at which the plurality of data read out of said plurality of memories are provided by said plurality of transmission circuits.

8. A memory output method as set forth in claim 7, wherein said control step includes the steps of:

feeding a read address to said plurality of memories so as to determine the delay times of said plurality of transmission circuits;

monitoring the individual data output timings of said plurality of transmission circuits; and

adjusting the individual delay times of said plurality of transmission circuits in accordance with results of said monitoring step.

9. A memory output method as set forth in claim 8, wherein said monitoring step comprises the steps of:

generating a standard signal indicating a standard timing, at which said plurality of data should reach said processor through said plurality of transmission circuits; and

monitoring the data output timings of said plurality of transmission circuits in terms of differences between the data output timings of said plurality of transmission circuits and the standard timing indicated by said standard signal.

10. A memory data output method as set forth in claim 9, wherein said monitoring the data output timing step includes the steps of:

selectively outputting one of a counting up signal and a counting down signal for each of said plurality of transmission circuits based upon one of the differences monitored for each of said plurality of transmission circuits,

wherein said adjusting step is performed by use of an UP/DOWN counter provided for each transmission circuit and responding to said one of said count up signal and said count down signal provided for said each transmission circuit,

wherein each of said transmission circuits comprises a variable delay circuit for delaying the data read out to the corresponding data bus with a delay time corresponding to a count value of the corresponding UP/DOWN counter;

wherein said step of feeding a read address is repeated at different times so that said monitoring step repeats outputting of one of a count up signal and a count down signal for each of said plurality of transmission circuits.

11. A memory data output method as set forth in claim 10, wherein said control step further comprises the steps of:

outputting an early signal and a delayed signal, which are shifted by a constant time period from said standard signal, and

wherein said monitoring the data output timings step includes a step of;

generating a count-up signal or a count-down signal from said standard signal, said early signal, said delayed signal and one of the data output by one of said transmission circuits.

12. A memory data output method as set forth in claim 8, further comprising the steps of:

receiving, by a plurality of flip-flops, the outputs of said plurality of transmission circuits in response to identical operating clocks of said processor and feeding the received signals to said processor,

wherein said monitoring the individual data output timings step includes the step of;

detecting the timings of changes of outputs of said flip-flops.

13. A data processing system comprising:

a processor;

a plurality of memories;

an address bus for transmitting an address fed from said processor to said plurality of memories;

a plurality of data buses provided individually for said plurality of memories for transmitting a plurality of data fed from said processor in parallel to said plurality of memories and for transmitting a plurality of data read out of said plurality of memories in parallel to said processor; and

a plurality of transmission circuits provided individually for said plurality of memories and capable of controlling delay times for feeding a plurality of data, which are read out of said plurality of memories to said plurality of data buses, with a delay to said processor.

14. A data processing system as set forth in claim 13, further comprising:

a control circuit for determining individual delay times of said plurality of transmission circuits so that the plurality of data read out of said plurality of memories for an identical address fed from said processor reach said processor within a predetermined time difference.

15. A data processing system as set forth in claim 14, wherein said control circuit comprises:

a circuit for controlling delay times of a plurality of variable delay circuits in response to data output timings of said plurality of transmission circuits for the plurality of data read out of said plurality of memories for the identical address fed from said processor change.

16. A data processing system as set forth in claim 14, wherein said control circuit comprises:

a circuit for controlling individual delay times of a plurality of transfer circuits so that the plurality of data read out of said plurality of memories for the identical address fed from said processor may individually reach said processor after a predetermined time has elapsed after said address is sent out to said address bus.

17. A data processing system as set forth in claim 15, wherein said control circuit further comprises:

means for feeding a read address to said plurality of memories so as to determine the delay times of said plurality of transmission circuits;

a plurality of monitor means for monitoring the individual timings at which the plurality of data read out of said plurality of memories for said fed read address reach said processor through said plurality of transmission circuits; and

means for determining the individual delay times of said plurality of transmission circuits in accordance with the monitor results of said plurality of monitor means.

18. A data processing system as set forth in claim 17, wherein said delay time determining means comprises:

means for generating a standard signal indicating the standard timing, at which said plurality of data should reach said processor through said plurality of transmission circuits;

means for changing the individual delay times of said plurality of transmission circuits based upon the difference between timings at which said plurality of data reach said processor, said timings being detected by said plurality of monitor means, and the standard timing indicated by said standard signal; and

means for repeating feeding of the address by said address feeding means, the monitoring by said plurality of monitor means and changing of the individual delay times by said delay time changing means until the plurality of data read out of said plurality of memories reaches said processor within a predetermined time difference.

19. A data processing system as set forth in claim 18, wherein each of said plurality of monitor means comprises a circuit for outputting a signal for counting up or down a delay time for each transmission circuit,

wherein said delay time changing means includes an UP/DOWN counter for each transmission circuit, responding to the counting up or down signal outputted by the corresponding one of said plurality of monitor means, and

wherein each of said transmission circuits comprises a variable delay circuit for delaying the data read out to the corresponding data bus with a delay time different in dependence upon the output of the corresponding UP/DOWN counter.

20. A data processing system as set forth in claim 19, wherein said control circuit further comprises:

means for outputting an early signal and a delayed signal, which are shifted by a constant time period from said standard signal, and

wherein said means for outputting the counting up or down signal comprises;

a circuit for generating a count-up signal or a count-down signal from said standard signal, an early signal, a delayed signal and the timing at which the data read out through the corresponding transmission circuit reaches said processor.

21. A data processing system as set forth in claim 14, wherein said plurality of transmission circuits and said control circuit are included in the same LSI as said processor.

22. A data processing system as set forth in claim 17, further comprising:

a plurality of flip-flops for receiving the outputs of said plurality of transmission circuits in response to the identical operating clocks of said processor and feeding the fetched signals to said processor,

wherein each of said plurality of monitor means comprises;

means for detecting a changing timing of an output of one of said flip-flops for receiving the outputs of the corresponding transmission circuits, to detect the timing at which the data reach said processor through said transmission circuits.

23. A data processing system comprising:

a circuit for outputting an address signal in synchronism with a clock signal;

at least one memory LSI for outputting a data signal in response to said address signal; and

a flip-flop for receiving the data signal outputted by said memory LSI, wherein the improvement comprises;

means for adjusting the time period for said data signal to reach said flip-flop by delaying it.

24. A data processing system as set forth in claim 23, wherein said adjusting means is controlled by a control signal.

25. A data processing system as set forth in claim 24, further, comprising:

means for storing said control signal.

26. A data processing system as set forth in claim 25, wherein said storing means, said flip-flop and said adjusting means are packaged in a common LSI.

27. A data processing system as set forth in any of the claims 24 to 26, further comprising:

means for generating said control signal automatically.

28. A data processing system as set forth in claim 27, wherein said generating means comprises:

means for deciding whether or not a change timing of the output of said flip-flop and a predetermined timing are within a predetermined difference.

29. A data processing system as set forth in either of the claim 27, wherein said generating means has means for changing a value of at least one of a plurality of bits of said address signal to provide different addresses to said LSI memory and means for causing said adjusting means to adjust the time periods for different data signals provided by said LSI memory for said different addresses to reach said flip-flop.

30. A data processing system as set forth in either of the claim 28, wherein said generating means has means for changing a value of at least one of a plurality of bits of said address signal to provide different addresses to said LSI memory and means for causing said adjusting means to adjust the time periods for different data signals provided by said LSI memory for said different addresses to reach said flip-flop.

31. A data processing system as set forth in any of the claims 23 to 26, further comprising:

means for changing, after said adjusting, a time difference between the timing at which said address signal is outputted and the timing at which said flip-flop receives said data signal; and

means for causing said adjusting means to repeat adjustment of said time period after said changing.

32. A data processing system as set forth in claim 27, further comprising:

means for changing, after said adjusting, a time difference between the timing at which said address signal is outputted and the timing at which said flip-flop receives said data signal; and

means for causing said adjusting means to repeat adjustment of said time period after said changing.

33. A data processing system as set forth in claim 28, further comprising:

means for changing, after said adjusting, a time difference between the timing at which said address signal is outputted and the timing at which said flip-flop receives said data signal; and

means for causing said adjusting means to repeat adjustment of said time period after said changing.

34. A data processing system as set forth in claim 29, further comprising:

means for changing, after said adjusting a time difference between the timing at which said address signal is outputted and the timing at which said flip-flop receives said data signal; and

means for causing said adjusting means to repeat adjustment of said time period after said changing.

35. A data processing system as set forth in any of the claims 23 to 26, wherein said adjusting means includes:

a synchronizing circuit for shifting the timing at which said data signal provided by said LSI memory reaches said flip-flop by an amount dependent upon a combination of a plurality of clocks applied thereto.

36. A data processing system as set forth in claim 27, wherein said adjusting means includes:

a synchronizing circuit for shifting the timing at which said data signal provided by said LSI memory reaches said flip-flop by an amount dependent upon a combination of a plurality of clocks applied thereto.

37. A data processing system as set forth in claim 28, wherein said adjusting means includes:

a synchronizing circuit for shifting the timing at which said data signal provided by said LSI memory reaches said flip-flop by an amount dependent upon a combination of a plurality of clocks applied thereto.

38. A data processing system as set forth in claim 29, wherein said adjusting means includes:

a synchronizing circuit for shifting the timing at which said data signal provided by said LSI memory reaches said flip-flop by an amount dependent upon a combination of a plurality of clocks applied thereto.

39. A data processing system as set forth in claims 30, wherein said adjusting means includes:

a synchronizing circuit for shifting the timing at which said data signal provided by said LSI memory reaches said flip-flop by an amount dependent upon a combination of a plurality of clocks applied thereto.

40. A data processing system as set forth in claim 31, wherein said adjusting means includes:

a synchronizing circuit for shifting the timing at which said data signal provided by said LSI memory reaches said flip-flop by an amount dependent upon a combination of a plurality of clocks applied thereto.

41. A data processing system as set forth in claim 23, wherein said adjusting means comprises:

a variable delay circuit.

42. A data processing system as set forth in claim 23, wherein said LSI memory comprises:

means for adjusting the timings at which output signals area provided by said LSI memory,

means for detecting the timing when the address signal has changed; and

means for supplying a control signal to said arranging means when a predetermined time elapses after said address signal has been outputted to said LSI memory wherein said adjusting means includes means for generating a data signal in response to said control signal and for providing said generated data signal in place of reading a data signal held at a location designated by said address signal within said LSI memory.

43. A data processing system as set forth in claim 42, further comprising:

means for preventing said supplying means from supplying said control signal when another address is outputted by said outputting means to said LSI memory after adjusting by said adjusting means is over;

wherein said adjusting means includes means for providing a data signal read out from a location within said LSI memory designated by said another address.

44. Apparatus, comprising:

a data processing system which comprises;

a processor,

a plurality of memories,

an address bus for transmitting addresses fed from said processor to said plurality of memories, and

a plurality of data buses provided individually for said plurality of memories for transmitting a plurality of data fed from said processor in parallel to said plurality of memories and for transmitting a plurality of data read out of said plurality of memories in parallel to said processor; and

a memory data output circuit for outputting data read out from said plurality of memories at substantially the same time, said memory data output circuit comprises;

a plurality of transmission circuits provided individually for said plurality of memories and capable of controlling delay time for feeding a plurality of data, which are read out of said plurality of memories to said plurality of data buses, with a delay to said processor.

45. A data processing system comprising:

a processor;

a plurality of memories;

an address bus for transmitting addresses fed from said processor to said plurality of memories;

a plurality of data buses provided individually for said plurality of memories for transmitting a plurality of data fed from said processor in parallel to said plurality of memories and for transmitting a plurality of data read out of said plurality of memories in parallel to said processor; and

a memory data output circuit for outputting data read out from said plurality of memories at substantially the same time, said memory data output circuit comprises;

a plurality of transmission circuits provided individually for said plurality of memories and capable of controlling delay times for feeding a plurality of data, which are read out of said plurality of memories to said plurality of data buses, with a delay to said processor.

46. A data processing system comprising:

a processor;

a plurality of memories;

an address bus for transmitting addresses fed from said processor to said plurality of memories;

a plurality of data buses provided individually for said plurality of memories for transmitting a plurality of data fed from said processor in parallel to said plurality of memories and for transmitting a plurality of data read out of said plurality of memories in parallel to said processor; and

a memory data output circuit for outputting data read out from said plurality of memories at substantially the same time, said memory data output circuit comprises;

a plurality of transmission circuits provided individually for said plurality of memories for transmitting from said plurality of memories via said plurality of data buses to said processor a plurality of data read out of said plurality of memories with adjustable delay times, and

a control circuit which adjusts delay times of said plurality of transmission circuits in response to data output timings of said plurality of transmission circuits at which the plurality of data read out of said plurality of memories are provided by said plurality of transmission circuits.