Static memory long write test
First Claim
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1. A method for performing a long write test on a static memory, comprising the steps of:
- writing a test data pattern to a plurality of memory cells, having a data contents, of a static memory, wherein each memory cell, having at least one wordline, is connected to a bitline true and a bitline complement;
turning off the wordline of each .memory cell of the plurality of memory cells during the long write test;
pulling both the bitline true and bitline complement connected to each memory cell of the plurality of memory cells down to a low logic level during the long write test;
exiting the long write test; and
reading the data contents of the plurality of memory cells to determine which of the plurality of memory cells contain corrupted data.
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Abstract
According to the present invention, after a test data pattern has been written to selected static memory cells, the wordlines of the memory cells are turned off and the bitline true and bitline complement of the memory cells are simultaneously pulled to a predetermined logic level for the duration of the long write test so that the memory cells are disturbed. After the long write test, the contents of the memory cells are read to determine which memory cells contain corrupted data and therefore have bitline to memory cell leakage problems.
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Citations
34 Claims
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1. A method for performing a long write test on a static memory, comprising the steps of:
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writing a test data pattern to a plurality of memory cells, having a data contents, of a static memory, wherein each memory cell, having at least one wordline, is connected to a bitline true and a bitline complement; turning off the wordline of each .memory cell of the plurality of memory cells during the long write test; pulling both the bitline true and bitline complement connected to each memory cell of the plurality of memory cells down to a low logic level during the long write test; exiting the long write test; and reading the data contents of the plurality of memory cells to determine which of the plurality of memory cells contain corrupted data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A memory structure which provides improved long write testing of a static memory, comprising:
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at least one wordline of a memory cell; a bitline true of the memory cell which is connected to a true bitline load element and a first pull-down transistor; a bitline complement of the memory cell which is connected to a complement bitline load element and a second pull-down transistor; a bus connected to the bitline true load element, the first pull-down transistor, the bitline complement load element, and the second pull-down transistor, wherein after data of a test data pattern has been written to the memory cell, the wordline is turned off during a long write test, and the bitline true and bitline complement are pulled down to a low logic level by forcing the bus to a predetermined logic level such that the bitline true load and the bitline complement load are turned off during the long write test. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. A memory structure which provides improved long write testing of a static memory, comprising:
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a bitline true connected to a first transistor of a memory cell; a bitline complement connected to a second transistor of the memory cell; a first passgate connected to the bitline true; a second passgate connected to the bitline complement; a column decode signal connected to the first passgate and the second passgate; a first write driver, having a first data input signal, which is connected to the first passgate; a second write driver, having a second data input signal, which is connected to the second passgate; and a wordline connected to the first transistor and the second transistor of the memory cell, wherein after data of a test data pattern has been written to the memory cell, the wordline is turned off during a long write test, and the bitline true and the bitline complement are pulled to a logic low level by setting the column decode signal to a predetermined logic level, thus turning on a column of the static memory such that the first write driver and the second write driver force the bitline true and the bitline complement to the logic low level. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34)
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Specification