Frequency and phase-locked two-phase digital synthesizer

• US 5,577,073 A
• Filed: 12/15/1994
• Issued: 11/19/1996
• Est. Priority Date: 09/07/1993
• Status: Expired due to Term

• Current Assignee: Emcore Corporation
• Original Assignee: Rockwell International Corporation
• Inventors: White, Stanley A.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): VO, DON NGUYEN
• Application Number:
  US08/356,934
• Time in Patent Office: 705 Days
• Field of Search: 375/324, 375/326, 375/327, 375/376, 331/30, 331/31, 331/187
• US Class Current: 375/324
• CPC Class Codes: G01C 19/5607 using vibrating tuning forks double-ended tuning forks using planar vibrating masses suspended at opposite ends G01C19/5719

Abstract

For use with a quartz angular rate sensor, a frequency and phase-locked synthesizer recovers a reference signal virtually free of phase noise, and generates a quadrature-phase reference signal for complex demodulation of the angular rate signal. The synthesizer also ensures a precisely adjusted phase shift of approximately zero across the drive tines of the sensor. Moreover, the digital synthesizer provides a precise numerical indication of the drive frequency, which can be used for compensation and automatic tuning of filters, such as a tracking filter, a filter in an automatic gain control, and notch filters in the phase and/or frequency detectors in the digital synthesizer. The tracking filter is used as a pre-filter for the synthesizer, and is responsive to a passband-width control signal generated from the magnitude of the frequency and phase error signal controlling the frequency generated by the synthesizer. Preferably the synthesizer has an oscillator controller for producing a pair of frequency control signals that are the sine and cosine of a frequency control parameter (φ), and one of these control signals is generated from the other by a polynomial approximation. To compensate for roundoff error, when one of the in-phase or quadrature-phase outputs has a magnitude less than a limit value, a compensated value for the other output is computed from an even polynomial of the magnitude.

Claims

1. A digital oscillator including an in-phase delay unit and a quadrature delay unit connected in a feedback circuit, said digital oscillator including a roundoff compensation system for computing a corrected value for an output of each delay unit based on a value of a filtered output of the other delay unit when the value of the filtered output of said other delay unit is within predetermined limits, the digital oscillator being of the two phase, that is, in-phase and quadrature phase, state variable type, with at least four multipliers, the roundoff compensation system comprising:

(a) means for eliminating the accumulation of roundoff error, such means comprising means for causing, when a magnitude of an output value of either phase is below a predetermined threshold, the output value of the other phase to be computed by a Chebyshev approximation;

(b) means for driving two of the four multipliers directly by a control input, x, and the other two multipliers by a Chebyshev approximation to (1-x²).sup. 1/2 ; and

(c) a pair of filters for reducing any noise generated by element (a), namely, an in-phase filter placed between the in-phase delay unit output and an in-phase roundoff compensation unit output, and a quadrature filter placed between the quadrature delay unit output and an quadrature roundoff compensation unit output, the coefficients for the filters being supplied under the direction of the control input x.

2. The digital oscillator of claim 1, wherein the coefficients supplied under the direction of the control input are supplied directly by the control input.

3. A digital sinusoidal synthesizer comprising:

(a) a digital oscillator including an in-phase delay unit and a quadrature delay unit connected in a feedback circuit, said digital oscillator including a roundoff compensation system for computing a corrected value for an output of each delay unit based on a value of a filtered output of the other delay unit When the value of the filtered output of said other delay unit is within predetermined limits, the digital oscillator being of the two phase, that is, in-phase and quadrature phase, state variable type, with at least four multipliers, the roundoff compensation system comprising;

(1) means for eliminating the accumulation of roundoff error, such means comprising means for causing, when a magnitude of an output value of either phase is below a predetermined threshold, the output value of the other phase to be computed by a Chebyshev approximation;

(2) means for driving two of the four multipliers directly by a control input, x, and the other two multipliers by a Chebyshev approximation to (1-x²).sup. 1/2 ; and

(3) a pair of filters for reducing any noise generated by element (a), namely, an in-phase filter placed between the in-phase delay unit output and an in-phase roundoff compensation unit output, and a quadrature filter placed between the quadrature delay unit output and a quadrature roundoff compensation unit output, the coefficients for the filters being supplied under the direction of the control input x;

(b) a discriminator having a reference input;

(c) a controller including a first accumulator, a saturating element, and a scaling multiplier, connected to take signals from the discriminator and pass them to the oscillator; and

(d) a feedback loop, including a filter whose parameters are set by the oscillator, from the output of the oscillator to the reference input of the discriminator.

4. The digital sinusoidal synthesizer of claim 3, wherein the feedback loop comprises an in-phase feedback loop and a quadrature feedback loop.

5. The digital sinusoidal synthesizer of claim 3, further comprising a phase shifter in the feedback loop.

6. The digital sinusoidal synthesizer of claim 5, wherein the feedback loop comprises an in-phase feedback loop and a quadrature feedback loop.

7. The digital sinusoidal synthesizer of claim 3, wherein the coefficients supplied under the direction of the control input are supplied directly by the control input.

8. The digital sinusoidal synthesizer of claim 7, wherein the feedback loop comprises an in-phase feedback loop and a quadrature feedback loop.

9. The digital sinusoidal synthesizer of claim 7, further comprising a phase shifter in the feedback loop.

10. The digital sinusoidal synthesizer of claim 9, wherein the feedback loop comprises an in-phase feedback loop and a quadrature feedback loop.

11. The digital sinusoidal synthesizer according to any of claims 3 through 10, wherein the discriminator comprises a combination of a frequency error detector for detecting the phase error in a downstream oscillator having an in-phase output and a quadrature output, a phase error detector, and a first summer,

(a) the phase error detector comprising:

(1) a first multiplier for multiplying the quadrature output (delayed for as many clock cycles, if any, as is necessary to account for the difference between the signal being fed to the detector and the signal to which it is desired for the oscillator to lock) and an input signal to the detector;

(2) an adjustable frequency notch filter, driven by an output of the first multiplier, the filter preferably comprising;

(A) a first delay element driving a first input of a second multiplier, a second input of the second multiplier being driven by a external frequency adjustment input; and

said first delay element also driving a second delay element; and

(B) a second summer, the second summer receiving (at a minus input) the output of the second multiplier, the output of the first multiplier being applied to a plus input of the second summer, and the output of the second delay element being applied to another plus input of the second summer; and

(3) a servo stabilizer driven by an output of the second summer, the stabilizer preferably comprising a lead lag network and a fixed gain;

(b) the frequency detector comprising;

(1) a pair of zero crossing detectors, one of which is driven by the input signal, and the other of which is driven by the in-phase channel feedback of the oscillator;

(2) a differencer for taking the difference between the outputs of the two zero crossing detectors;

(3) a second accumulator receiving the output of the differencer, the second accumulator preferably comprising a loop comprising a saturating element, a delay element, and a third summer, the third summer summing the input to the second accumulator with its output, which is the output of the delay element; and

(4) a servo stabilizer driven by the second accumulator, the stabilizer preferably comprising a lead lag network and a fixed gain; and

(c) the first summer being connected for summing an output of the phase error detector and an output of the frequency error detector, an output of the first summer forming a control signal for the oscillator.

12. The digital sinusoidal synthesizer according to any of claims 3 through 10, wherein the discriminator comprises:

(a) a phase error detector for detecting the phase error in a downstream oscillator having an in-phase output and a quadrature output, the detector comprising;

(1) a first multiplier for multiplying the quadrature output (delayed for as many clock cycles, if any, as is necessary to account for the difference between the signal being fed to the detector and the signal to which it is desired for the oscillator to lock) and an input signal to the detector;

(2) an adjustable frequency notch filter, driven by an output of the first multiplier,

(3) a servo stabilizer driven by an output of the adjustable frequency notch filter, the stabilizer preferably comprising a lead lag network and a fixed gain;

(b) a frequency error detector for detecting the frequency error in the downstream oscillator, the frequency detector comprising;

(1) a pair of zero crossing detectors, one of which is driven by the input signal, and the other of which is driven by the in-phase ;

channel feedback of the oscillator;

(2) a differencer for taking the difference between outputs of the two zero crossing detectors;

(3) a second accumulator receiving the output of the difference, the second accumulator preferably comprising a loop comprising a saturating element, a delay element, and a summer, the summer summing the input to the accumulator with its output, which is the output of the delay element; and

(4) a servo stabilizer driven by the second accumulator, the stabilizer preferably comprising a lead lag network and a fixed gain; and

(c) a second summer for summing an output of the phase error detector and an output of the frequency error detector, an output of the second summer forming a control signal for the oscillator.

13. The digital sinusoidal synthesizer according to any of claims 3 through 10, wherein:

(a) the discriminator comprises;

(1) a phase error detector for detecting the phase error in a downstream oscillator having an in-phase output and a quadrature output, the detector comprising;

(A) a first multiplier for multiplying the quadrature output (delayed for as many clock cycles, if any, as is necessary to account for the difference between the signal being fed to the detector and the signal to which it is desired for the oscillator to lock) and an input signal to the detector;

(B) an adjustable frequency notch filter, driven by an output of the first multiplier; and

(C) a servo stabilizer driven by an output of a first summer, the stabilizer preferably comprising a lead lag network and a fixed gain;

(2) frequency error detector for detecting the frequency error in the downstream oscillator, the frequency detector comprising;

(A) a pair of zero crossing detectors, one of which is driven by the input signal, and the other of which is driven by the in-phase channel feedback of the oscillator;

(B) a differencer for taking the difference between outputs of the two zero crossing detectors;

(C) a second accumulator receiving the output of the differencer, the Second accumulator preferably comprising a loop comprising a saturating clement, a delay element, and a second summer, the second summer summing the input to the second accumulator with its output, which is the output of the delay element; and

(D) a servo stabilizer driven by the second accumulator, the stabilizer preferably comprising a lead lag network and a fixed gain; and

(3) a third summer for summing an output of the phase error detector and an output of the frequency error detector, an output of the third summer forming a control signal for the oscillator; and

(b) the adjustable frequency notch filter comprises;

(1) a first delay element driving;

(A) a first input of a second multiplier, a second input of the second multiplier being driven by a external frequency adjustment input from an oscillator controller comprising a third accumulator;

a squaring element driven by the third accumulator;

means for multiplying, by four, an output of the squaring element; and

means for subtracting, by two, an output of the multiplying element; and

(B) a second delay element, and

(2) the first summer, the first summer receiving (at a minus input) the output of the second multiplier, the output of the first multiplier being applied to a plus input of the first summer, and the output of the second delay element being applied to another plus input of the first summer.

14. The digital sinusoidal synthesizer according to any of claims 3 through 10, wherein:

(a) the accumulator comprises;

(1) a first summer receiving, at a first input, an input to the accumulator;

(2) a saturator driven by the first summer; and

(3) a delay element driven by the saturator, an output of the delay element being connected to a second input to the first summer; and

(b) the discriminator further comprises;

(1) a frequency error detector for detecting the frequency error in the downstream oscillator, the frequency detector comprising;

(A) a pair of zero crossing detectors, one of which is driven by the input signal, and the other of which is driven by the in-phase channel feedback of the oscillator;

(B) a differencer for taking the difference between the outputs of the two zero crossing detectors;

(C) a second accumulator receiving the output of the differencer, the second accumulator preferably comprising a loop comprising a saturating element, a delay element, and a second summer, the second summer summing the input to the second accumulator with its output, which is the output of the delay element; and

(D) a servo stabilizer driven by the second accumulator, the stabilizer preferably comprising a lead lag network and a fixed gain; and

(2) a third summer for summing an output of a phase error detector and an output of the frequency error detector, an output of the third summer forming a control signal for the oscillator.

15. The digital sinusoidal synthesizer according to any of claim 3 through 10, wherein:

(a) the accumulator comprises;

(1) a first summer receiving, at a first input, an input to the accumulator;

(2) a saturator driven by the first;

summer; and

(3) a delay element driven by the saturator, an output of the delay element being connected to a second input to the first summer;

(b) the discriminator further comprises;

(1) a frequency error detector for detecting the frequency error in the downstream oscillator, the frequency detector comprising;

(A) a pair of zero crossing detectors, one of which is driven by the input signal, and the other of which is driven by the in-phase channel feedback of the oscillator;

(B) a differencer for taking the difference between the outputs of the two zero crossing detectors;

(C) a second accumulator receiving the output of the differencer, the second accumulator preferably comprising a loop comprising a saturating element, a delay element, and a second summer, the second summer summing the input to the second accumulator with its output, which is the output of the delay element; and

(D) a servo stabilizer driven by the second accumulator, the stabilizer preferably comprising a lead lag network and a fixed gain;

(2) a third summer for summing an output of a phase error detector and an output of the frequency error detector, an output of the third summer forming a control signal for the oscillator; and

(3) an adjustable frequency notch filter comprising;

(A) a first delay element driving;

(i) a first input of a second multiplier, a second input of the second multiplier being driven by a external frequency adjustment input from an oscillator controller comprising a third accumulator;

a squaring element driven by the third accumulator;

means for multiplying, by four, an output of the squaring element; and

means for subtracting, by two, an output of the multiplying element; and

(ii) a second delay element, and

(B) a fourth summer, the fourth summer receiving (at a minus input) the output of the second multiplier, the output of the first multiplier being applied to a plus input of the fourth summer, and the output of the second delay element being applied to another plus input of the fourth summer.

16. The digital sinusoidal synthesizer according to any of claims 3 through 10, wherein the discriminator comprises:

(a) an in-phase feedback loop and a quadrature phase feedback loop from a downstream oscillator, each loop comprising;

(1) an adjustable delay element;

(2) a multiplier receiving an input signal input and an output from the delay element; and

(3) an adjustable notch filter;

(b) a logic element having an output, wherein;

(1) the logic element is connected for receiving, at a clock cycle n;

(A) an output c(n) of the quadrature phase channel filter;

(B) an output d(n) of the in-phase channel filter;

(C) an output e of a zero crossing detector driven by the input signal; and

(D) an output f of a zero crossing detector driven by the delayed quadrature phase channel feedback signal; and

(2) the logic element is constructed for producing an output signal b(n+1) which is;

(A) c(n) if P0 is not true and P1 is not true and d(n) is greater than 0 and the sign of b(n) is the same as the sign of c(n), where b(n) is the output of the logic element from one clock cycle ago, P0 is true if f does not become true between consecutive true outputs of e, and P1 is true if e does not become true between consecutive true outputs of f;

(B) half the sign of c(n) if P0 is not true and P1 is not true and d(n) is less than zero and the sign of b(n) is the same as the sign of c(n);

(C) half of b(n) if the absolute value of b(n) is 1 and the sign of b(n) is not the same as the sign of c(n) and P0 is not true and P1 is not true;

(D) plus one-half if P0 is true; and

(E) minus one-half if P1 is true; and

(c) a controller comprising a servo stabilizer driven by the output of the logic element, the stabilizer preferably comprising a lead lag network, the stabilizer driving an accumulator, which in turn drives a fixed gain.

17. The digital sinusoidal synthesizer according to any of claims 3 through 10, wherein the discriminator comprises:

a first zero crossing detector receiving an in-phase feedback signal from a downstream oscillator, and producing an output signal Va;

(b) a second zero crossing detector receiving an input signal V3, and producing an output signal Vb;

(c) a first logic block receiving Va and Vb, and producing an output signal Vc such that;

(1) if two consecutive Vb are true, then Vc=+1;

(2) if two consecutive Va are true, then Vc=-1; and

(3) otherwise, Vc=0;

(d) an in-phase demodulator, receiving the in-phase feedback signal and modulating it by V3;

(e) a quadrature phase demodulator, receiving a quadrature phase feedback signal from the oscillator and modulating it by V3, and producing an output Vx;

(f) an in-phase limiter receiving an output of the in-phase demodulator, saturating at ±

1, and producing an output Vd;

(g) a quadrature phase limiter receiving Vx, saturating at ±

1, and producing an output Ve;

(h) a second logic block receiving Vc, Vd, and Ve, and producing an output signal Vf such that;

(1) Vf=+1 if;

(A) Vc=1;

or

(B) Vc=0 and Vd<

0 and Ve>

0;

(2) Vf=-1 if;

(A) Vc=-1;

or

(B) Vc=0 and Vd<

0 and Ve>

0; and

(3) otherwise, Vf=0;

(i) a third logic block receiving Vf and Vi, where Vi is Vf delayed by one clock cycle, and producing an output signal Vg such that;

(1) if Vf=Vi, then Vg=Vf; and

(2) otherwise, Vg=Vh, where Vh is Vg delayed by one clock cycle; and

(j) a fourth logic block receiving Vg and Vx, and producing an output signal Vj, an output of the discriminator, such that;

(j) a fourth logic block receiving Vg and Vx, and producing an output signal Vj, an output of the discriminator, such that;

(1) Vj=2(pi) if Vg=1

(2) Vj=-2(pi) ifVg=-1; and

(3) Vj=Vx if Vg=0.