Frame register switching for a video processor

• US 5,577,192 A
• Filed: 03/13/1996
• Issued: 11/19/1996
• Est. Priority Date: 11/01/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Frank, David C., Niederer, Theron P., Lee, William R.
• Primary Examiner(s): Tung, Kee Mei
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/616,243
• Time in Patent Office: 251 Days
• Field of Search: 395/162-166, 395/250, 395/425, 395/725, 395/775, 345/112, 345/119, 345/120, 345/201
• US Class Current: 345/519
• CPC Class Codes: G06F 5/16 Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Abstract

A video register interface for a video processor in which each frame register has a first storage element which is written by a microprocessor interface independently from a second storage element which outputs control data to video processing circuitry. Since reading and writing are done independently to different storage elements, the contents of the register can be changed without adverse effects on a displayed image. The register interface is used in a CMOS video processor which in turn is used in a microprocessor based multimedia computing system.

Claims

1. A video register interface for a video processor comprising:

at least two buffers, each buffer having first and second storage elements, the first storage element of a given buffer disposed to receive data from a microprocessor interface and to transfer that data to the second storage element of the given buffer, the second storage element of the given buffer disposed to receive data only from the first storage element of the given buffer;

logic for controlling timing of the transfer of data from the first storage element to the second storage element of the given buffer and for controlling outputting of data from the second storage element of the given buffer to video processing circuitry, the logic for controlling timing being connected to transfer mode control lines which allow the selection of one of a plurality of transfer modes, a selected transfer mode specifying the timing of the transfer from the first storage element to the second storage element of the given buffer; and

logic for selectively outputting data stored in the second storage element of a selected buffer to the video processing circuitry while allowing data in the first storage element of the selected buffer to be overwritten.

2. The video register interface of claim 1 wherein the logic for selectively outputting data comprises a selector.

3. A video processor integrated circuit comprising:

microprocessor interface circuitry for connection to a microprocessor bus;

video processing circuitry having means for receiving a video signal and means for outputting data to a video memory; and

a video register interface disposed between the microprocessor interface circuitry and the video processing circuitry, the video register interface including;

at least two buffers, each buffer having first and second storage elements, the first storage element of a given buffer disposed to receive data from the microprocessor interface circuitry and to transfer that data to the second storage element of the given buffer, the second storage element of the given buffer disposed to receive data only from the first storage element of the given buffer;

logic for controlling timing of the transfer of data from the first storage element to the second storage element of the given buffer and for controlling outputting of data from the second storage element of the given buffer to the video processing circuitry, the logic for controlling timing being connected to transfer mode control lines which allow the selection of one of a plurality of transfer modes, a selected transfer mode specifying the timing of the transfer from the first storage element to the second storage element of the given buffer; and

logic for selectively outputting data stored in the second storage element of a selected buffer to the video processing circuitry while allowing data in the first storage element of the selected buffer to be overwritten.

4. The video processor integrated circuit of claim 3 wherein the logic for selectively outputting data comprises a selector.

5. The video processor integrated circuit according to claim 3 or claim 4 wherein the video processing circuitry includes:

a digitizer interface circuit disposed to receive the video signal from a digitizer integrated circuit;

a codec interface circuit disposed to receive the video signal from a codec integrated circuit;

a video memory interface circuit for outputting the video data to the video memory; and

an image processor disposed between the digitizer and codec interface circuits and the video memory interface circuit.

6. An adapter card for use in a computer system, the adapter card comprising:

a video memory;

means for connection to a video display, the means connected to the video memory;

means for connection to a computer system bus; and

a video processor integrated circuit disposed between a video bus and the means for connection to the computer system bus, the video processor integrated circuit including;

microprocessor interface circuitry for connection to the system bus;

video processing circuitry having means for receiving a video signal and means for outputting data to the video memory; and

a video register interface disposed between the microprocessor interface circuitry and the video processing circuitry, the video register interface including;

at least two buffers, each buffer having first and second storage elements, the first storage element of a given buffer disposed to receive data from the microprocessor interface circuitry and to transfer that data to the second storage element of the given buffer, the second storage element of the given buffer disposed to receive data only from the first storage element of the given buffer;

logic for controlling timing of the transfer of data from the first storage element to the second storage element of the given buffer and for controlling outputting of data from the second storage element of the given buffer to the video processing circuitry, the logic for controlling timing being connected to transfer mode control lines which allow the selection of one of a plurality of transfer modes, a selected transfer mode specifying the timing of the transfer from first storage element to the second storage element of the given buffer; and

logic for selectively outputting data stored in the second storage element of a selected buffer to the video processing circuitry while allowing data in the first storage element of the selected buffer to be overwritten.

7. The adapter card of claim 6 wherein the logic for selectively outputting data comprises a selector.

8. The adapter card according to claim 6 or claim 7 wherein the video processing circuitry includes:

a digitizer interface circuit disposed to receive the video signal from a digitizer integrated circuit;

a codec integrated circuit disposed to receive the video signal from a codec integrated circuit;

a video memory interface circuit for outputting the video data to the video memory; and

an image processor disposed between the digitizer and codec interface circuit and the video memory interface circuit.

9. A computer system comprising:

a processor;

a storage means;

a system bus coupling the processor and the storage means to one or more adapter card connectors; and

at least one adapter card connected to the computer system through an adapter card connector, the adapter card including;

a video memory;

means for connection to a video display, the means connected to the video memory;

means for connection to a computer system bus; and

a video processor integrated circuit disposed between the video bus and the means for connection to the computer system bus, the video processor integrated circuit including;

microprocessor interface circuitry for connection to the system bus;

video processing circuitry having means for receiving a video signal and means for outputting data to the video memory; and

a video register interface disposed between the microprocessor interface circuitry and the video processing circuitry, the video register interface including;

at least two buffers, each having first and second storage elements, the first storage element of a given buffer disposed to receive data from the microprocessor interface circuitry and to transfer that data to the second storage element of the given buffer, the second storage element of the given buffer disposed to receive data only from the first storage element of the given buffer;

logic for controlling timing of the transfer of data from the first storage element to the second storage element of the given buffer and for controlling outputting of data from the second storage element of the given buffer to the video processing circuitry, the logic for controlling timing being connected to transfer mode control lines which allow the selection of one of a plurality of transfer modes, a selected transfer mode specifying the timing of the transfer from the first storage element to the second storage element of the given buffer; and

logic for selectively outputting data stored in the second storage element of a selected buffer to the video processing circuitry while allowing data in the first storage element of the selected buffer to be overwritten.