Computer system and method for pipelined transfer of data between modules utilizing a shared memory and a pipeline having a plurality of registers

• US 5,577,229 A
• Filed: 12/19/1994
• Issued: 11/19/1996
• Est. Priority Date: 01/30/1989
• Status: Expired due to Term

• Current Assignee: Ericsson AB (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Alantec Corp. (Cornhill Corp. Holdings LLP)
• Inventors: Wakerly, John F.
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/359,112
• Time in Patent Office: 701 Days
• Field of Search: 395/425, 395/325, 395/550, 395/400, 395/275, 395/458, 395/474, 395/475, 395/476, 395/477, 395/494, 395/495, 395/496, 395/405, 395/200.07, 395/200.08, 395/842 , 395/840, 395/872, 395/287, 395/290
• US Class Current: 711/147
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/36 for access to common bus or bus system

Abstract

A computer system and method for transferring data from a first memory to a second memory of a computer system are disclosed. The computer system includes a bus for transferring data between a first module and a second module, at least one of the modules including a shared memory having multiple ports. One port of each shared memory communicates with the bus through a pipeline which includes a plurality of registers connected in series. The pipeline allows shifting data in the registers by one register and loading data from the input of the pipeline into a first one of the registers. An access to one of the shared memories through one port is allowed to proceed simultaneously with a portion of a data transfer between the memories which includes a data transfer through another port and pipeline. The pipelines thus allow shared memories to communicate even when the memories are not simultaneously available for communication with each other.

Claims

1. A computer system comprising:

a first module;

a second module; and

a bus for transferring data between the first and second modules,

wherein the first module comprises;

a memory M1; and

a pipeline PL1 for transferring data from a port PRT1 of the memory M1 to the bus, the pipeline PL1 having an input for receiving data from the memory M1 and an output for providing data to the bus,

wherein the second module comprises;

a memory M2; and

a pipeline PL2 for transferring data from the bus to a port PRT2 of the memory M2, the pipeline PL2 having an input for receiving data from the bus and an output for providing data to the memory M2,

wherein at least one pipeline PLi (i=1 or

     2) of the pipelines PL1 and PL2 comprises a plurality of registers connected to each other in series, a first one of the registers being connected to the input of the pipeline PLi and wherein the pipeline PLi allows shifting data in the registers by one register and loading data from the input of the pipeline PLi into the first one of the registers, and

wherein at least one memory Mj (j=1 or

     2) of the memories M1 and M2 is a shared memory having a plurality of ports including port PRTj, wherein an access to the memory Mj through a port other than PRTj is allowed to proceed without a data transfer through the pipeline PLj and is allowed to proceed simultaneously with a portion of a data transfer from the memory M1 to the memory M2, the data transfer from M1 to M2 including a data transfer through the port PRTj and the pipeline PLj.

2. The computer system of claim 1 wherein the second module comprises means for asserting a ready signal to indicate that the second module is ready to accept data into the pipeline PL2, the second module negating the ready signal when such negation is needed to prevent the pipeline PL2 from overflowing.

3. The computer system of claim 1 wherein each of the memories M1 and M2 is a shared memory having a plurality of ports.

4. The computer system of claim 3 wherein:

the pipeline PLi is the pipeline PL1; and

the pipeline PL2 comprises a plurality of registers connected to each other in series, a first one of the registers of the pipeline PL2 being connected to the input of the pipeline PL2, and the pipeline PL2 allows shifting data in the registers of the pipeline PL2 by one register and loading data from the input of the pipeline PL2 into the first one of the registers of the pipeline PL2.

5. The computer system of claim 1 wherein:

the pipeline PLi is the pipeline PL1; and

the first module further comprises a pipeline PL11 for transferring data from the bus to the memory M1, the pipeline PL11 having an input for receiving data from the bus and an output for providing data to the memory M1, the pipeline PL11 comprising a plurality of registers connected in series to each other, a first one of the registers of the pipeline PL11 being connected to the input of the pipeline PL11, wherein the pipeline PL11 allows shifting data in the registers of the pipeline PL11 by one register and loading data from the input of the pipeline PL11 into the first one of the registers of the pipeline PL11.

6. The computer system of claim 5 wherein the pipeline PL11 is responsive to a signal to shift data in the registers of the pipeline PL11 by one register and to load data from the input of the pipeline PL11 into the first one of the registers of the pipeline PL11.

7. The computer system of claim 1 wherein the first module comprises means for asserting a request signal to request an access to the memory M1 through the port PRT1 the request signal being negated when such negation is needed to prevent the pipeline PL1 from overflowing.

8. The computer system of claim 9 wherein the second module comprises means for asserting a ready signal to indicate that the second module is ready to accept data into the pipeline PL2, the second module negating the ready signal when such negation is needed to prevent the pipeline PL2 from overflowing.

9. The computer system of claim 1 wherein the pipeline PLi is responsive to a signal S1 to shift data in the registers of the pipeline PLi by one register and to load data from the input of the pipeline PLi into the first one of the registers of the pipeline PLi.

10. The computer system of claim 9 further comprising means for providing to the pipeline PLi a clock signal such that at an end of a period of the clock signal, data in the pipeline PLi is shifted by one register, and data is loaded from the input of the pipeline PLi into the first one of the registers, if the signal S1 is asserted.

11. The computer system of claim 10 wherein a pipeline PLk which is one of the pipelines PL1 and PL2 and which is different from the pipeline PLi is responsive to a signal S2 to load data from the input of the pipeline PLk into the pipeline PLk such that at an end of a period of the clock signal, data is loaded from the input of the pipeline PLk into the pipeline PLk if the signal S2 is asserted.

12. The computer system of claim 1 wherein the memory Mj is the memory M1.

13. The computer system of claim 12 wherein the pipeline PLi is the pipeline PL2.

14. The computer system of claim 12 wherein an access to the memory M1 through a port other than PRT1 is allowed to proceed simultaneously with a data transfer from the pipeline PL1 to the pipeline PL2 through the bus even when the memory M1 is inaccessible through the port PRT1.

15. The computer system of claim 12 wherein an access to the memory M1 through a port other than PRT1 is allowed to proceed simultaneously with a data transfer from the pipeline PL2 to the port PRT2 even when the memory M1 is inaccessible through the port PRT1.

16. The computer system of claim 15 wherein an access to the memory M1 through a port other than PRT1 is allowed to proceed simultaneously with a data transfer from the pipeline PL1 to the pipeline PL2 through the bus even when the memory M1 is inaccessible through the port PRT1.

17. The computer system of claim 1 wherein the memory Mj is the memory M2.

18. The computer system of claim 17 wherein the pipeline PLi is the pipeline PL1.

19. The computer system of claim 17 wherein an access to the memory M2 through a port other than PRT2 is allowed to proceed simultaneously with a data transfer from the pipeline PL1 to the pipeline PL2 through the bus even when the memory M2 is inaccessible through the port PRT2.

20. The computer system of claim 17 wherein an access to the memory M2 through a port other than PRT2 is allowed to proceed simultaneously with a data transfer from the port PRT1 to the pipeline PL1 even when the memory M2 is inaccessible through the port PRT2.

21. The computer system of claim 20 wherein an access to the memory M2 through a port other than PRT2 is allowed to proceed simultaneously with a data transfer from the pipeline PL1 to the pipeline PL2 through the bus even when the memory M2 is inaccessible through the port PRT2.

22. A method for transferring data from a memory M1 to a memory M2, the method comprising the steps of:

transferring a word of data from a port PRT1 of the memory M1 to an input of a pipeline PL1;

loading said word of data from the input of the pipeline PL1 into the pipeline PL1;

transferring said word of data from the pipeline PL1 onto a bus;

providing said word of data from the bus to an input of a pipeline PL2;

loading said word of data from the input of the pipeline PL2 into the pipeline PL2; and

transferring said word of data from the pipeline PL2 to a port PRT2 of the memory M2,

wherein at least one pipeline PLi (i 32 1 or

     2) of the pipelines PL1 and PL2 comprises a plurality of registers connected to each other in series, the first one of the registers being connected to the input of the pipeline PLi, p1 wherein Loading a word of data into the pipeline PLi comprises (1) loading a word of data from the input of the pipeline PLi into the first one of the registers of the pipeline PLi, and (2) shifting data previously loaded into the pipeline PLi by one register, and

wherein at least one memory Mj (j=1 or

     2) of the memories M1 and M2 is a shared memory having a plurality of ports including port PRTj, wherein an access to the memory Mj through a port other than PRTj is allowed to proceed without a data transfer through the pipeline PLj and is allowed to proceed simultaneously with a portion of a data transfer from the memory M1 to the memory M2, the data transfer from M1 to M2 including a data transfer through the port PRTj and the pipeline PLj.

23. The method of claim 22 further comprising the steps of:

checking if loading said word of data into the pipeline PL2 could cause the pipeline PL2 to overflow;

if the checking step indicates that loading said word of data into the pipeline PL2 could cause the pipeline PL2 to overflow, then negating a ready signal to indicate that the second module is not ready to accept said word of data into the pipeline PL2.

24. The method of claim 22 wherein each of the memories M1 and M2 is a shared memory comprising a plurality of ports.

25. The method of claim 24 wherein:

the pipeline PLi is the pipeline PL1;

the pipeline PL2 comprises a plurality of registers connected to each other in series, the first one of the registers of the pipeline PL2 being connected to the input of the pipeline PL2; and

loading a word of data into the pipeline PL2 comprises (A) loading a word of data from the input of the pipeline PL2 into the first one of the registers of the pipeline PL2, and (B) shifting data previously loaded into the pipeline PL2 by one register.

26. The method of claim 22 further comprising, before the step of transferring a word of data from the port PRT1 to an input of the pipeline PL1, the steps of:

checking if loading said word of data into the pipeline PL1 could cause the pipeline PL1 to overflow; and

when the checking step indicates that loading said word of data into the pipeline PL1 could not cause the pipeline PL1 to overflow, then asserting a request signal to request an access to the memory M1 through the port PRT1.

27. The method of claim 26 further comprising the steps of:

(A) checking if loading said word of data into the pipeline PL2 could cause the pipeline PL2 to overflow;

(B) if the step (A) indicates that loading said word of data into the pipeline PL2 could cause the pipeline PL2 to overflow, then negating a ready signal to indicate that the second module is not ready to accept said word of data into the pipeline PL2.

28. The method of claim 22 wherein loading a word of data into the pipeline PLi further comprises the step of asserting a signal S1, and wherein the steps (1) and (2) are performed in response to the signal S1 being asserted.

29. The method of claim 28 further comprising the step of providing a clock signal to the pipeline PLi such that the steps (1) and (2) are performed on an edge of the clock signal.

30. The method of claim 29 wherein said edge of the clock signal is a rising edge.

31. The method of claim 22 wherein the memory Mj is the memory M1.

32. The method of claim 31 wherein the pipeline PLi is the pipeline PL2.

33. The method of claim 31 wherein an access to the memory M1 through a port other than PRT1 is allowed to proceed simultaneously with the steps of transferring said word of data from the pipeline PL1 onto the bus, providing said word of data from the bus to the input of the pipeline PL2, and loading said word of data from the input of the pipeline PL2 into the pipeline PL2, even when the memory M1 is inaccessible through the port PRT1.

34. The method of claim 31 wherein an access to the memory M1 through a port other than PRT1 is allowed to proceed simultaneously with transferring said word of data from the pipeline PL2 to the port PRT2 even when the memory M1 is inaccessible through the port PRT1.

35. The method of claim 34 wherein an access to the memory M1 through a port other than PRT1 is allowed to proceed simultaneously with the steps of transferring said word of data from the pipeline PL1 onto the bus, providing said word of data from the bus to the input of the pipeline PL2, and loading said word of data from the input of the pipeline PL2 into the pipeline PL2, even when the memory M1 is inaccessible through the port PRT1.

36. The method of claim 22 wherein the memory Mj is the memory M2.

37. The method of claim 36 wherein the pipeline PLi is the pipeline PL1.

38. The method of claim 36 wherein an access to the memory M2 through a port other than PRT2 is allowed to proceed simultaneously with the steps of transferring said word of data from the pipeline PL1 onto the bus, providing said word of data from the bus to the input of the pipeline PL2, and loading said word of data from the input of the pipeline PL2 into the pipeline PL2, even when the memory M2 is inaccessible through the port PRT2.

39. The method of claim 36 wherein an access to the memory M2 through a port other than PRT2 is allowed to proceed simultaneously with transferring said word of data from the port PRT1 to the input of the pipeline PL1 even when the memory M2 is inaccessible through the port PRT2.

40. The method of claim 39 wherein an access to the memory M2 through a port other than PRT2 is allowed to proceed simultaneously with the steps of transferring said word of data from the pipeline PL1 onto the bus, providing said word of data from the bus to the input of the pipeline PL2, and loading said word of data from the input of the pipeline PL2 into the pipeline PL2, even when the memory M2 is inaccessible through the port PRT2.