Parallel array processor interconnections
First Claim
1. An interconnection system for a plurality of processing elements (PEs) each having a plurality of I/O ports for transmitting and receiving data and instructions, the interconnection system comprising:
- coupling means for interconnecting the plurality of PEs, the 6 coupling means including all of the inter-PE couplings present in a square torus configuration having an equal number of PEs as in said plurality of PEs, the coupling means implementing half the number of inter-PE couplings required in the torus configuration by sharing each non-diagonal PE'"'"'s (PEij) I/O ports with its associated symmetrical PE (PEji), thereby forming a symmetric PE including PEij and PEji, where i and j are column and row designators, respectively, of corresponding PEs in the torus configuration, and where i and j are non-equal non-zero positive integers, andwherein the coupling means further includes means for transmitting and receiving data and instructions in one of four selectable modes;
a) transmit east/receive west mode for transmitting data to an east PE over a portion of the I/O ports while receiving data from a west PE over a remaining portion of the I/O ports;
b) transmit north/receive south mode for transmitting data to a north PE over a portion of the I/O ports while receiving data from a south PE over a remaining portion of the I/O ports;
c) transmit south/receive north mode for transmitting data to the south PE over a portion of the I/O ports while receiving data from the north PE over a remaining portion of the I/O ports; and
d) transmit west/receive east mode for transmitting data to the west PE over a portion of the I/O ports while receiving data from the east PE over a remaining portion of the I/O ports.
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Abstract
Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requirements is the mesh connected computer. Such a computer becomes a massively parallel machine when an array of computers interconnected by a network are replicated in a machine. The nearest neighbor mesh computer consists of an N×N square array of Processor Elements(PEs) where each PE is connected to the North, South, East and West PEs only. Assuming a single wire interface between PEs, there are a total of 2N2 wires in the mesh structure. Under the assumtion of SIMD operation with uni-directional message and data transfers between the processing elements in the meah, for example all PES transferring data North, it is possible to reconfigure the array by placing the symmetric processing elements together and sharing the north-south wires with the east-west wires, thereby reducing the wiring complexity in half, i.e. N2 without affecting performance. The resulting diagonal folded mesh array processor, which is called Oracle, allows the matrix transformation operation to be accomplished in one cycle by simple interchange of the data elements in the dual symmetric processor elements. The use of Oracle for a parallel 2-D convolution mechanish for image processing and multimedia applications and for a finite difference method of solving differential equations is presented, concentrating on the computational aspects of the algorithm.
39 Citations
9 Claims
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1. An interconnection system for a plurality of processing elements (PEs) each having a plurality of I/O ports for transmitting and receiving data and instructions, the interconnection system comprising:
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coupling means for interconnecting the plurality of PEs, the 6 coupling means including all of the inter-PE couplings present in a square torus configuration having an equal number of PEs as in said plurality of PEs, the coupling means implementing half the number of inter-PE couplings required in the torus configuration by sharing each non-diagonal PE'"'"'s (PEij) I/O ports with its associated symmetrical PE (PEji), thereby forming a symmetric PE including PEij and PEji, where i and j are column and row designators, respectively, of corresponding PEs in the torus configuration, and where i and j are non-equal non-zero positive integers, and wherein the coupling means further includes means for transmitting and receiving data and instructions in one of four selectable modes; a) transmit east/receive west mode for transmitting data to an east PE over a portion of the I/O ports while receiving data from a west PE over a remaining portion of the I/O ports; b) transmit north/receive south mode for transmitting data to a north PE over a portion of the I/O ports while receiving data from a south PE over a remaining portion of the I/O ports; c) transmit south/receive north mode for transmitting data to the south PE over a portion of the I/O ports while receiving data from the north PE over a remaining portion of the I/O ports; and d) transmit west/receive east mode for transmitting data to the west PE over a portion of the I/O ports while receiving data from the east PE over a remaining portion of the I/O ports. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification
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- Resources
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsDelgado-Fnias, Jose G., Pechanek, Gerald G., Vassiliadis, Stamatis
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Primary Examiner(s)Donaghue, Larry D.
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Application NumberUS08/522,163Time in Patent Office495 DaysField of Search395/800, 395/309, 395/27, 395/11, 395/20, 395/24, 395/27, 395/286, 395/287US Class Current712/11CPC Class CodesG06F 15/8023 Two dimensional arrays, e.g...G06N 3/063 using electronic meansG06N 3/10 Interfaces, programming lan...
