Vertical power MOSFET and process of fabricating the same

• US 5,578,508 A
• Filed: 04/21/1995
• Issued: 11/26/1996
• Est. Priority Date: 10/28/1993
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tsuchitani, Masanobu, Matsuda, Noboru, Baba, Yoshiro, Osawa, Akihiko, Yanagiya, Satoshi
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Dutton, Brian K.
• Application Number:
  US08/426,233
• Time in Patent Office: 585 Days
• Field of Search: 437/35, 437/67, 437/40 DM, 437/41 DM, 437/203, 437/45, 257/330, 257/331, 257/332, 257/333, 257/334
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Abstract

A channel region and a source region are formed on a surface of a substrate by double diffusion. A trench is formed so as to penetrate a part of the channel region and a part of the source region and reach the substrate. After an insulating film is formed on an inner wall of the trench, a polysilicon layer is buried up to an intermediate portion of the trench. In this state, channel ions are implanted in a side surface region of the trench, thereby depleting a channel region. Thereafter, a polysilicon layer for leading out a gate is buried in the trench.

Claims

1. A process of fabricating a vertical MOSFET comprising the steps of:

forming a first semiconductor layer of a first conductivity type on a major surface of a semiconductor substrate of the first conductivity type, said first semiconductor layer functioning as a drain region;

selectively introducing impurities of a second conductivity type into a surface region of the first semiconductor layer, thereby forming a second semiconductor layer of the second conductivity type functioning as a channel region;

selectively introducing impurities of the first conductivity type into a surface region of the second semiconductor layer, thereby forming a third semiconductor layer of the first conductivity type functioning as a source region;

forming at least one trench extending from the surface of the third semiconductor layer and penetrating the second semiconductor layer such that a bottom portion of said trench reaches the first semiconductor layer;

forming a first insulating film on at least the bottom portion of the trench;

depositing an ion implantation mask layer on said first insulating film such that said trench is filled, and etching back said ion implantation mask layer so that said ion implantation mask layer remains up to an intermediate portion of said trench;

removing that portion of the first insulating film, which is exposed to the trench;

implanting channel ions into an exposed inner wall of the trench in a slanting direction;

forming a second insulating film on said ion implantation mask layer and on the exposed inner wall of said trench, said second insulating film functioning as a gate insulating film;

depositing a conductor layer entirely on the second insulating film such that said trench is filled; and

removing said conductor layer such that said conductor layer is left at least in said trench, thereby forming a gate lead-out electrode.

2. The process according to claim 1, wherein said step of forming said first semiconductor layer is carried out by an epitaxial growth method.

3. The process according to claim 1, wherein said step of burying the ion implantation mask layer on the first insulating film up to the intermediate portion of said trench comprises the sub-steps of:

a first sub-step of depositing said ion implantation mask layer over the entire surface; and

a second sub-step of etching back said ion implantation mask layer.

4. The process according to claim 1, wherein said step of implanting channel ions into the exposed inner wall of the trench in the slanting direction is carried out while said semiconductor substrate is being rotated.

5. The process according to claim 1, further comprising the steps of:

forming a third insulating film covering continuously said gate lead-out electrode, the surface of said first semiconductor layer, the surface of said second semiconductor layer and the surface of said third semiconductor layer;

forming first and second contact holes in said third insulating film;

depositing a metallic layer over the resultant structure and patterning said metallic layer, thereby forming a gate electrode put in contact with said gate lead-out electrode via the first contact hole and a source electrode put in contact with the surface of said second semiconductor layer and the surface of said third semiconductor layer via said second contact hole; and

forming a drain electrode on a bottom surface of said semiconductor substrate.

6. A process of fabricating a semiconductor device, comprising the steps of:

selectively introducing impurities of a second conductivity type into a surface region of a first semiconductor layer of a first conductivity type, thereby forming a second semiconductor layer of the second conductivity type;

forming at least one trench extending from the surface of the second semiconductor layer and penetrating said second semiconductor layer such that a bottom portion of said trench reaches the first semiconductor layer;

forming a first insulating layer on at least the bottom portion of said trench;

depositing an ion implantation mask layer on said first insulating film such that said trench is filled, and etching back said ion implantation mask layer so that said ion implantation mask layer remains up to an intermediate portion of said trench;

removing a portion the first insulating film, which is exposed to the trench; and

implanting channel ions into an exposed inner wall of the trench in a slanting direction.

7. The process according to claim 6, wherein said step of burying the ion implantation mask layer on the first insulating film up to the intermediate portion of said trench comprises the sub-steps of:

a first sub-step of depositing an ion implantation mask layer over the entire surface; and

a second sub-step of etching back said ion implantation mask layer.

8. The process according to claim 6, wherein a said step of implanting channel ions into the exposed inner wall of the trench in the slanting direction is carried out while substrate on which said first semiconductor layer is formed.

9. The process according to claim 6, further comprising the steps of:

forming a second insulating film on said ion implantation mask layer and inner wall of the exposed trench;

deposition a conductor layer entirely on the second insulating film such that said trench is filled; and

removing said conductor layer such that said conductor layer is left at least in said trench, thereby forming an electrode.