Semiconductor device and method of fabricating same

• US 5,578,522 A
• Filed: 11/30/1995
• Issued: 11/26/1996
• Est. Priority Date: 02/24/1994
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nakamura, Katsumi, Minato, Tadaharu, Shiozawa, Katsuomi, Tominaga, Shuuichi
• Primary Examiner(s): Dang, Trung
• Application Number:
  US08/565,277
• Time in Patent Office: 362 Days
• Field of Search: 437/186, 437/191, 437/203, 437/31, 437/32, 437/982, 437/947, 148/DIG. 50, 148/DIG. 11, 148/DIG. 133
• US Class Current: 438/138
• CPC Class Codes: H01L 29/41716 Cathode or anode electrodes for thyristors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 148/011 Bipolar transistors
• CPC Class Codes: Y10S 148/05 Etch and refill
• CPC Class Codes: Y10S 148/133 Reflow oxides and glasses
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A semiconductor device including a layer formed without being affected by a stepped ground pattern and a method of fabricating the semiconductor device are disclosed. Cap portions (30) (insulating layers) formed over trenches (13) and covering doped polysilicon (5) have an inclined surface (26) which satisfies Y/X <5 where X is the length of the inclined surface (26) in a direction of the surface of a body (50) and Y is the height of the inclined surface (26) from the surface of the body (50). Formation of the insulating layers having the smooth inclined surface satisfying Y/X<5 permits a first main electrode to be formed nondefectively without being affected by the ground pattern including the insulating layers.

Claims

1. A method of fabricating a semiconductor device, comprising the steps of:

(a) providing a body of semiconductor having first and second major surfaces;

(b) selectively forming a plurality of trench portions extending from the first major surface of said body to a predetermined depth;

(c) forming a plurality of control electrode layers filling said plurality of trench portions, respectively, and extending over part of the first major surface of said body, the operation of said device being controlled by a control voltage applied commonly to said plurality of control electrode layers after completion of said device;

(d) forming an insulating layer on the first major surface of said body including said plurality of control electrode layers;

(e) patterning said insulating layer to form an opening in a predetermined position; and

(f) performing heat treatment upon said patterned insulating layer to form a smooth inclined surface adjacent said opening of said insulating layer,

wherein the heat treatment in said step (f) is carried out above a temperature at which said insulating layer is softened.

2. The method of claim 1,

wherein said inclined surface of said insulating layer satisfies

the conditional expression:

Y/X≦

5

where X is a length of said inclined surface in a direction of the first major surface of said body and Y is a height of said inclined surface from the first major surface of said body.

3. The method of claim 1,

wherein said control electrode layers and said insulating layer satisfy the conditional expression:

H2≧

H1

where H1 is a height of said control electrode layers formed over said part of the first major surface of said body from the first major surface of said body and H2 is a height of said insulating layer from the first major surface of said body.

4. The method of claim 1,

wherein said plurality of trench portions are spaced a predetermined distance apart from each other, and

the conditional expression:

(W/H)≦

8

is satisfied where W is said predetermined distance and H is a height of said insulating layer over said trench portions from the first major surface of said body.

5. The method of claim 1,

wherein said step (a) includes the steps of:

(a-1) providing a first semiconductor layer having first and second major surfaces;

(a-2) forming a first semiconductor region of a first conductivity type on the first major surface of said first semiconductor layer; and

(a-3) forming a second semiconductor region of a second conductivity type on said first semiconductor region, the second major surface of said first semiconductor layer being specified as the second major surface of said body, said second semiconductor region having a surface specified as the first major surface of said body, and

wherein the predetermined depth in said step (b) is a depth extending from the surface of said second semiconductor region through said second and first semiconductor regions.

6. The method of claim 5,

wherein said step (a-1) includes the steps of:

(a-1-1) providing a second semiconductor layer of the first conductivity type having first and second major surfaces; and

(a-1-2) forming a third semiconductor layer adjacent the first major surface of said second semiconductor layer, said third semiconductor layer being intrinsic or of the second conductivity type, said third and second semiconductor layers forming said first semiconductor layer, the second major surface of said second semiconductor layer being specified as the second major surface of said body.

7. The method of claim 1, further comprising the step of:

(g) performing heat treatment upon said insulating layer to flatten a surface of said insulating layer after said step (d),

wherein the heat treatment in said step (g) is carried out above a temperature at which said insulating layer is softened.

8. A method of fabricating a semiconductor device, comprising the steps of:

(a) providing a body of semiconductor having first and second major surfaces;

(b) selectively forming a plurality of trench portions extending from the first major surface of said body to a predetermined depth;

(c) forming a plurality of control electrode layers filling said plurality of trench portions, respectively, and extending over part of the first major surface of said body, the operation of said device being controlled by a control voltage applied commonly to said plurality of control electrode layers after completion of said device;

(d) forming an insulating layer on the first major surface of said body including said plurality of control electrode layers;

(e) performing heat treatment upon said insulating layer to flatten a surface of said insulating layer;

(f) forming an overlying insulating layer on said insulating layer;

(g) forming a resist on said overlying insulating layer;

(h) patterning said resist;

(i) etching said insulating layer and said overlaying insulating layer, using said patterned resist as a mask, to form an opening in a predetermined position; and

(j) performing heat treatment upon said etched insulating layer and overlying insulating layer to form a smooth inclined surface adjacent said opening of said insulating layer and overlaying insulating layer,

wherein the heat treatment in said steps (e) and (i) is carried out above a temperature at which at least said insulating layer is softened, and

wherein said overlaying insulating layer is more adherent to said resist than said insulating layer.

9. The method of claim 8,

wherein said etching in said step (i) is one of isotropic and anisotropic etchings.

10. The method of claim 8,

wherein said step (a) includes the steps of:

(a-1) providing a first semiconductor layer having first and second major surfaces;

(a-2) forming a first semiconductor region of a first conductivity type on the first major surface of said first semiconductor layer; and

(a-3) forming a second semiconductor region of a second conductivity type on said first semiconductor region, the second major surface of said first semiconductor layer being specified as the second major surface of said body, said second semiconductor region having a surface specified as the first major surface of said body, and

wherein the predetermined depth in said step (b) is a depth extending from the surface of said second semiconductor region through said second and first semiconductor regions.

11. The method of claim 10,

wherein said step (a-1) includes the steps of:

(a-1-1) providing a second semiconductor layer of the first conductivity type having first and second major surfaces; and

(a-1-2) forming a third semiconductor layer adjacent the first major surface of said second semiconductor layer, said third semiconductor layer being intrinsic or of the second conductivity type, said third and second semiconductor layers forming said first semiconductor layer, the second major surface of said second semiconductor layer being specified as the second major surface of said body.

12. The method of claim 8,

wherein said inclined surface of said insulating layer satisfies the conditional expression:

Y/X≦

5

where X is a length of said inclined surface in a direction of the first major surface of said body and Y is a height of said inclined surface from the first major surface of said body.

13. The method of claim 8,

wherein said control electrode layers and said insulating layer satisfy the conditional expression:

H2≧

H1

where H1 is a height of said control electrode layers formed over said part of the first major surface of said body from the first major surface of said body and H2 is a height of said insulating layer from the first major surface of said body.

14. The method of claim 8,

wherein said control electrode layers and said insulating layer satisfy both

the conditional expression:

Y/X≦

5 and

the conditional expression;

H2≧

H1

where X is a length of said inclined surface in a direction of the first major surface of said body, Y is a height of said inclined surface from the first major surface of said body, H1 is a height of said control electrode layers formed over said part of the first major surface of said body from the first major surface of said body, and H2 is a height of said insulating layer from the first major surface of said body.

15. The method of claim 8,

wherein said plurality of trench portions are spaced a predetermined distance apart from each other, and

the conditional expression:

(W/H)≦

8

is satisfied where W is said predetermined distance and H is a height of said insulating layer over said trench portions from the first major surface of said body.

16. The method of claim 8,

wherein said insulating layer includes a ground insulating layer and a major insulating layer, and

wherein said step (d) includes the steps of:

(d-1) forming said ground insulating layer on said plurality of control electrode layers; and

(d-2) forming said major insulating layer on the first major surface of said body including said ground insulating layer.

17. The method of claim 8,

wherein said step (i) includes the steps of:

(i-1) performing isotropic etching upon at least said overlying insulating layer, using said patterned resist as a mask; and

(i-2) performing anisotropic etching upon at least said insulating layer, using said patterned resist as a mask, to form an opening in a predetermined position of said overlying insulating layer and said insulating layer after the step (i-1).

18. The method of claim 17,

wherein said step (c) includes the steps of:

(c-1) forming an insulating film completely covering inner walls of said plurality of trench portions and extending over part of the first major surface of said body; and

(c-2) forming said plurality of control electrode layers respectively filling said plurality of trench portions, with said insulting film sandwiched between said control electrode layers and the inner walls of said trench portions, and extending over said part of the first major surface of said body, with said insulating film sandwiched between said control electrode layers and said body.

19. A method of fabricating a semiconductor device, comprising the steps of:

(a) providing a body having first and second major surfaces and including an upper layer portion adjacent the first major surface and a lower layer portion adjacent said second major surface, said upper layer portion being made of semiconductor of a first conductivity type, and then forming an MOS structure including a plurality of first semiconductor regions of a second conductivity type selectively formed in said upper layer portion of said body, a plurality of second semiconductor regions of the first conductivity type selectively formed in respective surfaces of said plurality of first semiconductor regions, a plurality of insulating films each formed on one of said first semiconductor regions between said upper layer portion of said body and said second semiconductor regions, and a plurality of control electrodes formed on said plurality of insulating films, respectively;

(b) forming an insulating layer on the first major surface of said body including said plurality of control electrodes;

(c) patterning said insulating layer to form an opening in a predetermined position;

(d) performing heat treatment upon said patterned insulating layer to form a smooth inclined surface adjacent said opening of said insulating layer;

(e) forming a first main electrode over the first major surface of said body; and

(f) forming a second main electrode on the second major surface of said body,

wherein a control voltage applied commonly to said plurality of control electrodes after completion of said device controls current between said first and second main electrodes, and

wherein the heat treatment in said step (d) is carried out above a temperature at which said insulating layer is softened.

20. The method of claim 19,

wherein said lower layer portion of said body is of the second conductivity type.

21. The method of claim 19,

wherein said inclined surface of said insulating layer satisfies the conditional expression:

Y/X≦

5

where X is a length of said inclined surface in a direction of the first major surface of said body and Y is a height of said inclined surface from the first major surface of said body.

22. The method of claim 19,

wherein said plurality of control electrodes are spaced a predetermined distance apart from each other, and

the conditional expression:

(W/H)≦

8

is satisfied where W is said predetermined distance and H is a height of said insulating layer from the first major surface of said body.

23. The method of claim 19,

wherein said plurality of control electrodes are spaced a predetermined distance apart from each other, and said control electrodes and said insulating layer satisfy

the conditional expression:

Y/X≦

5 and

the conditional expression;

(W/H)≧

8

where W is said predetermined distance, H is a height of said insulating layer from the first major surface of said body, X is a length of said inclined surface in a direction of the first major surface of said body, and Y is a height of said inclined surface from the first major surface of said body.