Vertical MOSFET device having frontside and backside contacts

• US 5,578,841 A
• Filed: 12/18/1995
• Issued: 11/26/1996
• Est. Priority Date: 12/18/1995
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Pages, Irenee M., Vasquez, Barbara, Prendergast, E. James
• Primary Examiner(s): WHITEHEAD JR, CARL W
• Application Number:
  US08/573,979
• Time in Patent Office: 344 Days
• Field of Search: 257/213, 257/220, 257/236, 257/242, 257/263, 257/278, 257/302, 257/341, 257/734, 257/737, 257/738, 257/778, 257/780
• US Class Current: 257/220
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A multiple output, vertical MOSFET device (11) with improved electrical performance and thermal dissipation is integrated with an additional semiconductor device or semiconductor circuit (18) on a single semiconductor substrate (34). The method of making the vertical MOSFET device (11) involves thinning the semiconductor substrate (34) after fabricating the vertical MOSFET device (11) and the semiconductor circuit (18) to reduce the vertical component of electrical and thermal resistance and to increase the thermal dissipation efficiency. Electrical performance is improved by thinning the semiconductor substrate (34) and by providing a low resistivity, patterned metal buried layer. Thermal management is enhanced by using flip chip bumps (24) to dissipate heat from a top surface (31) of the semiconductor substrate (34) and by using the patterned buried metal layer (26) to dissipate heat from a bottom surface (32) of the semiconductor substrate (34).

Claims

1. A vertical MOSFET device, comprising:

a semiconductor substrate with a first side and a second side opposite the first side;

an epitaxial layer over the first side, wherein the epitaxial layer has a source region, a drain region, and a channel region which couples the source region to the drain region, wherein the semiconductor substrate and the epitaxial layer have a combined thickness of approximately 20-100 microns;

a source electrode electrically coupled to the source region, the source electrode located over the first side of the semiconductor substrate;

a gate electrode over the channel region, the gate electrode located over the first side of the semiconductor substrate;

a drain electrode coupled to the second side of the semiconductor substrate;

flip chip bumps over the source electrode and the gate electrode; and

an assembly substrate electrically coupled to the flip chip bumps.

2. The vertical MOSFET device according to claim 1, further comprising a wire bond wire to electrically couple the drain electrode to the assembly substrate, wherein the drain electrode is patterned.

3. The vertical MOSFET device according to claim 2, wherein the semiconductor substrate comprises silicon and wherein the drain electrode is selected from the group consisting of aluminum or copper.

4. The vertical MOSFET device according to claim 1, wherein the drain electrode is unpatterned.

5. An electronic device with improved heat dissipation, the electronic device comprising:

a semiconductor substrate with a first side and a second side which are opposite to each other, wherein the semiconductor substrate has a source region, a drain region, and a channel region, wherein the channel region couples the source region to the drain region, and wherein the semiconductor substrate is approximately 20 to 100 microns thick;

a gate electrode over the channel region and located at the first side of the semiconductor substrate;

a source electrode electrically coupled to the source region and located at the first side of the semiconductor substrate; and

a buried metal layer coupled to the drain region, the buried metal layer selected from the group consisting of aluminum, copper, or conductive epoxy.

6. The electronic device according to claim 5, further comprising a semiconductor device in the semiconductor substrate, wherein the semiconductor substrate includes silicon.

7. The electronic device according to claim 5, further comprising a drain electrode coupled to the first side of the semiconductor substrate.

8. The electronic device according to claim 5, further comprising:

an assembly substrate; and

flip chip bumps electrically coupling the source electrode and the gate electrode to the assembly substrate.

9. The electronic device according to claim 8, further comprising a drain electrode coupled to the second side of the semiconductor substrate.

10. The electronic device according to claim 9, wherein the drain electrode is patterned and wherein the electronic device is a multiple output device.

11. The electronic device according to claim 9, wherein the drain electrode is unpatterned and wherein the electronic device is a single output device.

12. The electronic device according to claim 9 further comprising a wire bond wire to electrically couple the drain electrode to the assembly substrate.

13. A multiple output device with improved heat dissipation electrically coupled to an assembly substrate, the multiple output device comprising:

a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite the first surface;

a first region of a first conductivity type in the semiconductor substrate;

a second region of a second conductivity type in the first region;

a third region of the first conductivity type in the second region, wherein the second region separates the first region from the third region;

a first electrode at the first surface over the third region and electrically coupled to the third region;

a second electrode at the first surface and located over a portion of the second region to modulate a voltage potential of the portion of the second region to control current flow through the portion of the second region between the first region and the third region;

a third electrode at the second surface of the semiconductor substrate to remove heat from the second surface of the semiconductor substrate;

a first flip chip bump over the first electrode to electrically couple and to remove heat from the first surface of the semiconductor substrate to the assembly substrate;

a second flip chip bump over the second electrode to electrically couple and to remove heat from the first surface of the semiconductor substrate to the assembly substrate; and

a wire bond wire coupled to the third electrode to electrically couple the third electrode to the assembly substrate.

14. The multiple output device according to claim 13, wherein the third electrode is patterned.

15. The multiple output device according to claim 13, further comprising a semiconductor device in the semiconductor substrate with additional flip chip bumps over the first surface of the semiconductor substrate to couple the semiconductor device to the assembly substrate.

16. The multiple output device according to claim 15, wherein the semiconductor substrate is about 20 to 100 microns thick to improve heat dissipation from the semiconductor substrate.