Semiconductor memory cell having information storage transistor and switching transistor

• US 5,578,853 A
• Filed: 10/11/1995
• Issued: 11/26/1996
• Est. Priority Date: 12/10/1992
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Matsushita, Takeshi, Hayashi, Yutaka
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/541,172
• Time in Patent Office: 412 Days
• Field of Search: 257/351, 257/369, 257/401
• US Class Current: 257/351
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR₁ comprising a semiconductor channel layer Ch₁, first and second conductive gates G₁, G₂, and first and second conductive layers L₁, L₂ ; and a switching transistor TR₂ comprising a semiconductor channel forming region Ch₂, a third conductive gate G₃, and third and fourth conductive layers L₃, L₄, wherein the fourth conductive layer L₄ is connected to the second conductive gate G₂, the first conductive gate G₁ and the third conductive gate G₃ are connected to a first memory-cell-selection line, the first conductive layer L₁ and the third conductive layer L₃ are connected to a second memory-cell-selection line, the second conductive layer L₂ is connected to a fixed potential, and the semiconductor channel forming region Ch₂ is connected to a read/write selection line.

Claims

1. A semiconductor memory cell comprising:

a first semiconductor region of a first conductivity type formed in a surface region of a semiconductor substrate or on an insulating substrate,

a first conductive region formed in a surface region of said first semiconductor region in contacting relationship forming a rectifier junction therebetween,

a second semiconductor region of a second conductivity type formed in a surface region of said first semiconductor region but spaced apart from said first conductive region,

a second conductive region formed in a surface region of said second semiconductor region in contacting relationship forming a rectifier junction therebetween, and

a conductive gate disposed in such a manner as to form a bridge over a barrier layer between said first semiconductor region and said second conductive region and between said first conductive region and said second conductive region, wherein

said conductive gate is connected to a first memory-cell-selection line, and

said first semiconductor region is connected to a second memory-cell-selection line.