Semiconductor device having a plurality of semiconductor chips

• US 5,579,208 A
• Filed: 06/02/1995
• Issued: 11/26/1996
• Est. Priority Date: 07/09/1993
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited, Kyushu Fujitsu Electronics Ltd. (Fujitsu Limited)
• Original Assignee: Fujitsu Limited, Kyushu Fujitsu Electronics Ltd. (Fujitsu Limited)
• Inventors: Haranosono, Takao, Honda, Tosiyuki
• Primary Examiner(s): Ledynh, Bot L.
• Application Number:
  US08/459,689
• Time in Patent Office: 543 Days
• Field of Search: 361/728-730, 361/735, 361/813, 174/52.2, 257/777-778, 257/787-788, 257/791-794, 257/685-686, 437/208, 437/211-213, 437/219-220
• US Class Current: 361/813
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/07802 not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A chip-on chip type semiconductor device is provided in which semiconductor chips provided in a package cannot be displaced during a transfer molding process so as to eliminate a short circuit. At least two lead frames are provided in and extend from the package so that the first semiconductor chip and the second semiconductor chip can be electrically connected to external devices. A die stage is provided between the first semiconductor chip and the second semiconductor chip. A bonding wire is provided for wiring between the first semiconductor chip and the lead frames, and TAB leads connect the second semiconductor chip to the lead frames. The lead frames may extend between the first and second semiconductor devices instead of the die stage. The lead frames may include one having a portion extending in a direction perpendicular to the longitudinal direction of the lead frames between the first and second semiconductor chips.

Claims

1. A semiconductor device comprising:

a package having at least a first semiconductor chip and a second semiconductor chip, said first semiconductor chip being positioned above said second semiconductor chip;

at least a first lead frame and a second lead frame provided between said first and second semiconductor chips, and extending from said package so that said first semiconductor chip and said second semiconductor chip can be electrically connected to external devices, said first lead frame extending from a first side of said first and second semiconductor chips to a second side opposite to said first side of said first and second semiconductor chips, said second lead frame extending from said second side to said first side;

first connecting means for connecting first semiconductor chip to said first and second lead frames; and

second connecting means for connecting said second semiconductor chip to said first and second lead frames, wherein said first connecting means comprises a first TAB lead and said second connecting means comprises a second TAB lead, and wherein said first semiconductor chip is positioned so that a surface on which circuitry is provided faces downwardly, a first insulating member being provided between said first TAB lead and said first and second lead frames, and said second semiconductor chip is positioned so that a surface on which circuitry is provided faces upwardly, a second insulating member being provided between said second TAB lead and said first and second lead frames.

2. The semiconductor device as claimed in claim 1, wherein said first insulating member is formed of a portion of a TAB tape used for forming said first TAB tape, and said second insulating member is formed of a portion of a TAB tape used for forming said second TAB lead.

3. A semiconductor device comprising:

a package having at least a first semiconductor chip and a second semiconductor chip, said first semiconductor chip being positioned above said second semiconductor chip;

at least a first lead frame, a second lead frame and a third lead frame being provided between said first and second semiconductor chips, and extending from said package so that said first semiconductor chip and said second semiconductor chip can be electrically connected to external devices, said first lead frame extending a predetermined length from a first side of said first and second semiconductor chips, said second lead frame extending from a second side opposite to said first side of said first and second semiconductor chips, a space being formed between an end of said first lead frame and an end of said second lead frame and between said first semiconductor chip and said second semiconductor chip, said third lead frame having a portion extending in said space in a direction perpendicular to the longitudinal direction of said first and second lead frames;

at least one first TAB lead connecting said first semiconductor chip to a corresponding one of said first and third lead frames; and

at least one second TAB lead connecting said second semiconductor chip to a corresponding one of said second and third lead frames.

4. The semiconductor device as claimed in claim 3, wherein said first semiconductor chip is positioned so that a surface on which circuitry is provided faces upward, a first insulating member being provided between said first semiconductor chip and said first, second and third lead frames, and said second semiconductor chip is positioned so that a surface on which circuitry is provided faces downward, a second insulating member being provided between said second semiconductor chip and said first, second and third lead frames.

5. The semiconductor device as claimed in claim 3, wherein said first semiconductor chip is positioned so that a surface on which circuitry is provided faces upward, a first insulating member being provided between said first semiconductor chip and said first, second and third lead frames, and said second semiconductor chip is positioned so that a surface on which circuitry is provided faces upward, a second insulating member being provided between said second TAB lead and said first, second and third lead frames.

6. A semiconductor device comprising:

a package having at least a first semiconductor chip and a second semiconductor chip, said first semiconductor chip being positioned above said second semiconductor chip;

at least a first lead frame and a second lead frame provided between said first and second semiconductor chips, and extending from said package so that said first semiconductor chip and said second semiconductor chip can be electrically connected to external devices, said first lead frame extending from a first side of said first and second semiconductor chips to a second side opposite to said first side of said first and second semiconductor chips, said second lead frame extending from said second side to said first side;

first connecting means for connecting said first semiconductor chip to said first and second lead frames; and

second connecting means for connecting said second semiconductor chip to said first and second lead frames, wherein;

said first semiconductor chip is positioned so that a surface on which circuitry is provided faces upwardly, a first insulating member being provided between said first semiconductor chip and said first and second lead frames,

said second semiconductor chip is positioned so that a surface on which circuitry is provided faces downwardly, a second insulating member being provided between said second semiconductor chip and said first and second lead frames, and

each of said first and second connecting means comprises a TAB lead.

7. A semiconductor device comprising:

a package having at least a first semiconductor chip and a second semiconductor chip, said first semiconductor chip being positioned above said second semiconductor chip;

at least a first lead frame and a second lead frame provided between said first and second semiconductor chips, and extending from said package so that said first semiconductor chip and said second semiconductor chip can be electrically connected to external devices, said first lead frame extending from a first side of said first and second semiconductor chips to a second side opposite to said first side of said first and second semiconductor chips, said second lead frame extending from said second side to said first side;

first connecting means for connecting said first semiconductor chip to said first and second lead frames; and

second connecting means for connecting said second semiconductor chip to said first and second lead frames, wherein;

said first semiconductor chip is positioned so that a surface on which circuitry is provided faces upwardly, a first insulating member being provided between said first semiconductor chip and said first and second lead frames,

said second semiconductor chip is positioned so that a surface on which circuitry is provided faces downwardly, a second insulating member being provided between said second semiconductor chip and said first and second lead frames, and

said first connecting means comprises a bonding wire and said second connecting means comprises a TAB lead.