Interface controller for frame buffer random access memory devices

• US 5,579,473 A
• Filed: 07/18/1994
• Issued: 11/26/1996
• Est. Priority Date: 07/18/1994
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Deering, Michael F., Lavelle, Michael G., Kubalska, Ewa M., Schlapp, Stephen A.
• Primary Examiner(s): TUNG, KEE M
• Application Number:
  US08/276,814
• Time in Patent Office: 862 Days
• Field of Search: 395/162-166, 395/403, 395/445, 395/446-449, 345/185, 345/201
• US Class Current: 345/557
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A frame buffer memory device controller that schedules and dispatches operations to frame buffer memory devices is disclosed. The frame buffer memory device controller schedules and dispatches cache control operations to reduce timing overheads caused by cache prefetch operations, and operations to write back dirty cache lines and clear cache lines in the frame buffer memory devices. The frame buffer memory device controller also schedules and dispatches control operations to reduce timing overheads caused by video refresh operations from the frame buffer memory devices video output ports.

Claims

1. A frame buffer memory device controller coupled to receive a pixel access transaction targeted for pixel data mapped in at least one frame buffer memory device, the frame buffer memory device controller having circuitry for determining a cache state of the frame buffer memory device based on previous pixel access transactions, and circuitry for scheduling a cache transfer operation and for dispatching the cache transfer operation to the frame buffer memory device before dispatching the pixel access transaction to the frame buffer memory device.

2. The frame buffer memory device controller of claim 1, wherein the cache state of the frame buffer memory device indicates whether the pixel data is mapped to a level one pixel cache in the frame buffer memory device.

3. The frame buffer memory device controller of claim 2, wherein the cache transfer operation causes the frame buffer memory device to map the pixel data to the level one pixel cache if the cache state indicates that the pixel data is not mapped to the level one pixel cache.

4. The frame buffer memory device controller of claim 3, wherein the cache transfer operation causes the frame buffer memory device to transfer the pixel data between the level one pixel cache and a level two pixel cache in the frame buffer memory device.

5. The frame buffer memory device controller of claim 1, wherein the cache state of the frame buffer memory device indicates whether the pixel data is mapped to a level two pixel cache in the frame buffer memory device.

6. The frame buffer memory device controller of claim 5, wherein the cache transfer operation causes the frame buffer memory device to map the pixel data to the level two pixel cache if the cache state indicates that the pixel data is not mapped to the level two pixel cache.

7. The frame buffer memory device controller of claim 6, wherein the cache transfer operation causes the frame buffer memory device to transfer the pixel data between the level two pixel cache and a dynamic random access memory (DRAM) core in the frame buffer memory device.

8. The frame buffer memory device controller of claim 7, wherein the cache transfer operation causes the frame buffer memory device to transfer the pixel data into a video buffer from the level two pixel cache in the frame buffer memory device.

9. A frame buffer memory device controller coupled to receive a sequence of pixel access transactions targeted for pixel data mapped in at least one frame buffer memory device, the frame buffer memory device controller having circuitry for examining the sequence of pixel access transactions, and circuitry for scheduling a series of cache transfer operations in the frame buffer memory device to accommodate the sequence of pixel access transactions, and having circuitry for dispatching the cache transfer operations to the frame buffer memory device ahead of the pixel access transactions to the frame buffer memory device such that the cache transfer operations prevent stalls in the sequence of pixel access transactions to the frame buffer memory device.

10. The frame buffer memory device controller of claim 9, wherein the cache transfer operations include a level one cache operation that causes the frame buffer memory device to map the pixel data to a level one pixel cache in the frame buffer memory device.

11. The frame buffer memory device controller of claim 10, wherein the level one cache operation causes the frame buffer memory device to transfer the pixel data between the level one pixel cache and a level two pixel cache in the frame buffer memory device.

12. The frame buffer memory device controller of claim 11, wherein the cache transfer operations include a level two cache operation that causes the frame buffer memory device to map the pixel data to the level two pixel cache.

13. The frame buffer memory device controller of claim 12, wherein the level two cache operation causes the frame buffer memory device to transfer the pixel data between the level two pixel cache and a dynamic random access memory (DRAM) core in the frame buffer memory device.

14. The frame buffer memory device controller of claim 13, wherein the level two cache operation is dispatched ahead of the level one cache operation and wherein the level one cache operation is dispatched ahead of the corresponding pixel access transaction.

15. The frame buffer memory device controller of claim 9, wherein the cache transfer operations include a video transfer operation that causes the frame buffer memory device to transfer the pixel data into a video buffer from the level two pixel cache in the frame buffer memory device.

16. A frame buffer memory device controller comprising:

a translator, wherein said translator receives pixel access transactions targeted for pixel data mapped in a frame buffer memory device and converts said pixel access transactions into access parameters for said frame buffer memory device;

an allocator coupled to said translator, wherein said allocator receives said access parameters from said translator and determines a cache state of said frame buffer memory device based on previous pixel access transactions;

a scheduler coupled to said allocator, wherein said scheduler buffers requests received from said allocator,

an arbiter coupled to said scheduler and a video request generator, wherein said arbiter receives instructions from said scheduler and said video request generator and issues requests to said frame buffer memory device such that a cache transfer operation to said frame buffer memory device is performed before dispatching said pixel access transaction to said frame buffer memory device.

17. The frame buffer memory device controller of claim 16, wherein said translator receives a pixel address, an operation code and pixel data and further wherein said translator converts said pixel address into a corresponding address in said frame buffer memory device.

18. The frame buffer memory device controller of claim 16, wherein said allocator determines whether any changes are required to cache states of said frame buffer memory device.

19. The frame buffer memory device controller of claim 18, wherein said allocator determines whether any changes are required to caches states of a first level cache and a second level cache in said frame buffer memory device.

20. The frame buffer memory device controller of claim 19, wherein said scheduler buffers first level cache requests, second level cache requests and pixel access parameters in a first memory queue, a second memory queue and a third memory queue, respectively.

21. The frame buffer memory device controller of claim 20, wherein said memory queues operate independently such that a second level cache request is enabled to push ahead of a first level cache request.

22. The frame buffer memory device controller of claim 20, wherein said memory queues operate independently such that a first level cache request is enabled to push ahead of a pixel access parameter.

23. The frame buffer memory device controller of claim 20, wherein said arbiter arbitrates said first level cache requests, said second level cache requests and video access requests and issues said first level cache requests, said second level cache requests and said video access requests as dynamic random access memory requests on a dynamic random access memory bus.