Dynamic non-volatile memory update in a computer system

• US 5,579,522 A
• Filed: 07/24/1995
• Issued: 11/26/1996
• Est. Priority Date: 05/06/1991
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gabel, Douglas L., Murphy, Sean T., Christeson, Orville H.
• Primary Examiner(s): Kriess, Kevin A.
• Assistant Examiner(s): BUTLER, DENNIS
• Application Number:
  US08/505,995
• Time in Patent Office: 491 Days
• Field of Search: 395/700, 364/280.2, 364/280.9
• US Class Current: 713/2
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 8/656 while running

Abstract

A computer system wherein a portion of code/data stored in a non-volatile memory device can be dynamically modified or updated without removing any covers or parts from the computer system. The computer system of the preferred embodiment includes a flash memory component coupled to a computer system bus for storing non-volatile code and data. Using the present invention, the contents of a portion of the flash memory may be replaced, modified, updated, or reprogrammed without the need for removing and/or replacing any computer system hardware components. The flash memory device used in the preferred embodiment contains four separately erasable/programmable non-symmetrical blocks of memory. One of these four blocks may be electronically locked to prevent erasure or modification of its contents once it is installed. This configuration allows the processing logic of the computer system to update or modify any selected block of memory without affecting the contents of other blocks. One memory block contains a normal BIOS. An electronically protected flash memory area is used for storage of a recovery BIOS which is used for recovery operations. The present invention also includes hardware for selecting one of the two available update modes: normal or recovery. Thus, using a mode selection apparatus, either a normal system BIOS or a recovery BIOS may be activated.

Claims

1. A computer system comprising:

a processor for executing processing logic;

a programmable non-volatile semiconductor memory device coupled to said processor, said programmable non-volatile semiconductor memory device having BIOS firmware programmed therein, portions of said programmable non-volatile semiconductor memory device being write modifiable;

a random access memory (RAM) device coupled to said processor;

means for transferring a first portion of said BIOS firmware from said programmable non-volatile semiconductor memory device to said RAM, said first portion being specifically directed to updating other portions of said programmable non-volatile semiconductor memory device, said means for transferring coupled to said processor;

means for erasing a portion of said programmable non-volatile semiconductor memory device, said means for erasing coupled to said processor; and

,

means for updating a second portion of said BIOS firmware in said programmable non-volatile semiconductor memory while said first portion of said BIOS firmware is executing from said RAM, said means for updating coupled to said processor.

2. The computer system as claimed in claim 1 wherein said programmable non-volatile semiconductor memory device is a flash semiconductor memory device.

3. The computer system as claimed in claim 1 wherein said programmable non-volatile semiconductor memory device is partitioned into at least two separately erasable and programmable partitions, a first partition storing recovery processing logic and data, a second partition storing normal operating system processing logic and data.

4. The computer system as claimed in claim 1 wherein said firmware is a basic input/output system (BIOS).

5. The computer system as claimed in claim 1 said means for updating further including:

means for selecting an update type, said update type being either a normal update type or a recovery update type, said means for selecting coupled to said processor.

6. The computer system as claimed in claim 3, wherein said means for updating further including:

means for selecting an update type, said update type being either a normal update type or a recovery update type, said means for selecting coupled to said processor;

normal update processing logic operably disposed in said random access memory;

means for activating said normal update processing logic if said normal update type is selected by said means for selecting; and

means for reprogramming said second partition if said normal update processing logic is activated.

7. The computer system as claimed in claim 6 said means for reprogramming further including:

protected update processing logic residing within said normal operating system processing logic stored in said second partition;

means for transferring said protected update processing logic to said random access memory; and

means for activating said protected update processing logic, said protected update processing logic controlling the programming of said second partition.

8. The computer system as claimed in claim 3 said means for updating further including:

means for selecting an update type, said update type being either a normal update type or a recovery update type, said means for selecting coupled to said processor;

means for activating said recovery processing logic if said recovery update type is selected by said means for selecting an update type; and

means for reprogramming said second partition if said recovery processing logic is activated.

9. The computer system as claimed in claim 3 wherein said first partition is electronically protected from erasure or modification.

10. A computer system comprising:

a processor for executing processing logic;

a programmable non-volatile semiconductor memory device coupled to said processor, said programmable non-volatile semiconductor memory device having BIOS firmware programmed therein, portions of said programmable non-volatile semiconductor memory device being write modifiable;

a random access memory (RAM) device coupled to said processor;

means for transferring a first portion of said BIOS firmware from said programmable non-volatile semiconductor memory device to said RAM, said first portion being specifically directed to updating other portions of said programmable non-volatile semiconductor memory device, said means for transferring coupled to said processor;

means for erasing a portion of said programmable non-volatile semiconductor memory device, said means for erasing coupled to said processor; and

,

means for updating application specific BIOS firmware residing in a second portion of said programmable non-volatile semiconductor memory device while said first portion of said BIOS firmware is executing from said RAM, said means for updating coupled to said processor.

11. The computer system as claimed in claim 10 further including means for enabling scanning of said second portion of said programmable non-volatile semiconductor memory device containing application specific firmware.

12. The computer system as claimed in claim 10 wherein said application specific firmware includes LAN processing logic.

13. The computer system as claimed in claim 10 wherein said application specific firmware includes SCSI processing logic.

14. In a computer system having a processor for executing processing logic, a random access memory (RAM) coupled to said processor and a programmable non-volatile semiconductor memory device coupled to said processor, said programmable non-volatile semiconductor memory device having firmware programmed therein, portions of said programmable non-volatile semiconductor memory device being write modifiable, said firmware including a first portion programmed into an electronically write protected area of said programmable non-volatile semiconductor memory device, said first portion being specifically directed to updating said programmable non-volatile semiconductor memory device, a process for updating portions of said programmable non-volatile semiconductor memory device while said firmware is executing from said RAM, said process comprising the steps of:

transferring said first portion from said electronically protected area of said programmable non-volatile semiconductor memory device to said RAM;

executing said first portion to update a second portion of said programmable non-volatile semiconductor memory device; and

updating said second portion while said first portion is executing from said RAM.

15. The process as claimed in claim 14, said process further including the steps of:

selecting whether said first portion or said second portion is initially executed;

transferring said second portion from an unprotected area of said programmable non-volatile semiconductor memory device to said RAM, said step of transferring said second portion being performed if said second portion is selected for initial execution in said selecting step;

executing said second portion from said RAM if said second portion is selected for initial execution in said selecting step; and

executing said first portion from said RAM if said first portion is selected for initial execution in said selecting step.

16. The process of claim 15, wherein said second portion of said programmable non-volatile semiconductor memory device includes a second version of operating system firmware.

17. The process of claim 15, wherein said second portion of said programmable non-volatile semiconductor memory device includes application specific processing logic.

18. In a computer system having a processor for executing processing logic, a random access memory (RAM) coupled to said processor and a programmable non-volatile semiconductor memory device coupled to said processor, said programmable non-volatile semiconductor memory device having operating system firmware programmed therein, portions of said programmable non-volatile semiconductor memory device being write modifiable, a process for updating application specific firmware residing in a portion of said programmable non-volatile semiconductor memory device while said operating system firmware is executing, said process comprising the steps of:

transferring a first portion of said operating system firmware from said programmable non-volatile semiconductor memory device to said RAM, said first portion being specifically directed to reprogramming portions of said programmable non-volatile semiconductor memory device; and

executing said first portion of said operating system firmware to reprogram a second portion of said programmable non-volatile semiconductor memory device with application specific firmware.

19. The process as claimed in claim 18 further including a step of enabling scanning of said second portion of said programmable non-volatile semiconductor memory device containing application specific firmware.

20. The process as claimed in claim 18 wherein said application specific firmware includes LAN processing logic.

21. The process as claimed in claim 18 wherein said application specific firmware includes SCSI processing logic.

22. A computer system comprising:

a processor for executing logic instructions;

a programmable flash memory electrically connected to said processor, said programmable flash memory subdivided into a first part and a second part;

said first part of said programmable flash memory stores BIOS instructions for a normal update mode, wherein said normal update mode includes the instructions needed to save, verify, or update areas of flash memory including said second part of said programmable flash memory;

said second part of said programmable flash memory stores BIOS instructions for a recovery update mode, wherein said recovery update mode includes instructions needed to start the computer system and update the first part of said programmable flash memory.

23. The computer system described in claim 22, wherein said computer system includes a hardware device for selecting either said normal update mode or said recovery update mode.

24. The computer system of claim 23 wherein said hardware device is a jumper cable.

25. A method of updating a BIOS stored in a programmable non-volatile semiconductor memory device in a computer, said method comprising the steps of:

creating two portions of BIOS, a normal update portion and a recovery update portion and storing each portion in a section of said programmable non-volatile semiconductor memory device;

using a hardware device to switch between two start-up modes in said computer;

choosing to load into RAM memory either said normal update portion of BIOS or said recovery update portion of BIOS depending on setting of said hardware device;

loading the chosen portion of BIOS into said RAM memory; and

updating the portion of BIOS not loaded into said RAM memory.